Patents by Inventor Eietsu Takahashi

Eietsu Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240347113
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
  • Patent number: 12068040
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: August 20, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
  • Publication number: 20240153560
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI
  • Publication number: 20240105272
    Abstract: A semiconductor memory device includes: a first bit line connected to a first string including memory cell transistors; a second bit line connected to a second string including memory cell transistors; a source line connected to the first string and the second string; a word line connected to gates of the memory cell transistors in same rows of the first and strings; a voltage generation circuit configured to apply a first voltage to the first bit line according to a first target level, apply a second voltage to the second bit line according to a second target level, and apply a third voltage to the source line; and a row decoder configured to apply a fourth voltage to the word line to which a first memory cell transistor of the first string and a second memory cell transistor of the second string are connected during a verification operation.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 28, 2024
    Inventor: Eietsu TAKAHASHI
  • Patent number: 11915756
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 27, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Publication number: 20240005999
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
  • Patent number: 11817155
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: November 14, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
  • Publication number: 20230197167
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 22, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
  • Patent number: 11621041
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 4, 2023
    Assignee: Kioxia Corporation
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
  • Patent number: 11486767
    Abstract: A semiconductor storage device includes a memory cell and a control circuit configured to, upon receipt of a command, acquire a first temperature measured by a temperature sensor, and perform an operation corresponding to the command using a parameter corrected based on temperature. When the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature. When the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Keisuke Terada, Eietsu Takahashi
  • Publication number: 20220262439
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI
  • Patent number: 11355193
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: June 7, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Publication number: 20220065702
    Abstract: A semiconductor storage device includes a memory cell and a control circuit configured to, upon receipt of a command, acquire a first temperature measured by a temperature sensor, and perform an operation corresponding to the command using a parameter corrected based on temperature. When the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature. When the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.
    Type: Application
    Filed: March 1, 2021
    Publication date: March 3, 2022
    Inventors: Keisuke TERADA, Eietsu TAKAHASHI
  • Publication number: 20210217481
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Application
    Filed: March 31, 2021
    Publication date: July 15, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
  • Patent number: 11004520
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
  • Publication number: 20210020249
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Application
    Filed: October 6, 2020
    Publication date: January 21, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI
  • Publication number: 20210005270
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
  • Patent number: 10839908
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Kobayashi, Yoichi Minemura, Eietsu Takahashi, Masaki Kondo, Daisuke Hagishima
  • Patent number: 10832777
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Patent number: 10818362
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 27, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno