Patents by Inventor Eietsu Takahashi

Eietsu Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8605514
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory cell, a second memory cell, and a control circuit. The first memory cell is connected to a first word line. The second memory cell is connected to a second word line which is adjacent to the first word line and has a width different from a width of the first word line. The control circuit applies a first voltage to the first word line and a second voltage different from the first voltage to the second word line. At least one of the first voltage and the second voltage is corrected by the control circuit based on write loop counts of the first memory cell and the second memory cell when the first memory cell and the second memory cell are write target cells in a write operation.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Patent number: 8599617
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Publication number: 20130301359
    Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Yasuhiro SHIINO, Daisuke KOUNO, Shigefumi IRIEDA, Kenri NAKAI, Eietsu TAKAHASHI
  • Publication number: 20130242666
    Abstract: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo IZUMI, Eietsu Takahashi
  • Patent number: 8531891
    Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
  • Publication number: 20130229873
    Abstract: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number<the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.
    Type: Application
    Filed: April 17, 2013
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koki UENO, Eietsu Takahashi, Shigefumi Irieda, Yasuhiro Shiino, Manabu Sakaniwa
  • Patent number: 8446777
    Abstract: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number<the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: May 21, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koki Ueno, Eietsu Takahashi, Shigefumi Irieda, Yasuhiro Shiino, Manabu Sakaniwa
  • Patent number: 8422301
    Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Yuji Takeuchi
  • Publication number: 20130077409
    Abstract: A nonvolatile semiconductor storage device according to an embodiment includes: a memory cell array including plural memory cells; and a control circuit that repeatedly performs a write loop including a program operation and a verify operation in data write performed to the memory cell, the verify operation including a preverify step to check whether a threshold voltage of the memory cell transitions to a preverify voltage, and a real verify step to check whether the threshold voltage of the memory cell transitions to the real verify voltage, the write loop including one or at least two verify operations corresponding to pieces of the data, the control circuit performing the write loop in which the preverify step of the verify operation corresponding to a first data is omitted after obtaining a first condition.
    Type: Application
    Filed: April 20, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro SHIINO, Eietsu Takahashi
  • Publication number: 20130058170
    Abstract: A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.
    Type: Application
    Filed: March 12, 2012
    Publication date: March 7, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro SHIINO, Eietsu Takahashi, Yuji Takeuchi
  • Publication number: 20130058171
    Abstract: A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates. In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
    Type: Application
    Filed: March 20, 2012
    Publication date: March 7, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro SHIINO, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi, Koki Ueno
  • Patent number: 8385126
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: February 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
  • Publication number: 20120281487
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of memory cell units which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series, a voltage generator circuit which generates a voltage to be applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit. The control circuit, when writing data into the memory cell array, performs control so as to apply a first write pass voltage to unselected word lines in the memory cell units and, after a selected word line has reached a write voltage, further apply a voltage to the unselected word lines until a second write pass voltage higher than the first write pass voltage has been reached.
    Type: Application
    Filed: November 3, 2011
    Publication date: November 8, 2012
    Inventors: Manabu SAKANIWA, Koki Ueno, Shigefumi Irieda, Eietsu Takahashi, Yasuhiro Shiino
  • Publication number: 20120281477
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of cell units each composed of a plurality of memory cells which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series and select transistors each connected to either end of the series connection, a voltage generator circuit which generates a voltage applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit.
    Type: Application
    Filed: December 1, 2011
    Publication date: November 8, 2012
    Inventors: Manabu Sakaniwa, Koki Ueno, Shigefumi Irieda, Eietsu Takahashi, Yasuhiro Shiino, Daisuke Kouno
  • Publication number: 20120269001
    Abstract: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number<the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.
    Type: Application
    Filed: October 25, 2011
    Publication date: October 25, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koki UENO, Eietsu Takahashi, Shigefumi Irieda, Yasuhiro Shiino, Manabu Sakaniwa
  • Publication number: 20120257453
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Application
    Filed: September 27, 2011
    Publication date: October 11, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
  • Publication number: 20120206968
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Application
    Filed: April 27, 2012
    Publication date: August 16, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Publication number: 20120206972
    Abstract: A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.
    Type: Application
    Filed: September 7, 2011
    Publication date: August 16, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
  • Patent number: 8199579
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Publication number: 20120106257
    Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
    Type: Application
    Filed: January 10, 2012
    Publication date: May 3, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro SHIINO, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi