Patents by Inventor Eietsu Takahashi
Eietsu Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200043558Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: October 9, 2019Publication date: February 6, 2020Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu Takahashi, Koki Ueno
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Publication number: 20200013466Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: ApplicationFiled: September 18, 2019Publication date: January 9, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro SHIINO, Eietsu Takahashi
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Patent number: 10522227Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.Type: GrantFiled: March 9, 2018Date of Patent: December 31, 2019Assignee: Toshiba Memory CorporationInventors: Takashi Kobayashi, Yoichi Minemura, Eietsu Takahashi, Masaki Kondo, Daisuke Hagishima
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Patent number: 10490286Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: December 4, 2018Date of Patent: November 26, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Patent number: 10460806Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: GrantFiled: July 2, 2018Date of Patent: October 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi
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Publication number: 20190287640Abstract: A memory system includes a nonvolatile memory which includes a memory cell array, and a memory controller which includes a first ECC circuit, and a second ECC circuit having an error correction capability higher than that of the first ECC circuit, and is configured to perform ECC operation on data read from the nonvolatile memory using the first ECC circuit and the ECC circuit. During the ECC operation, the first ECC circuit corrects an error in first read data which is read out of the nonvolatile memory. The memory controller determines whether the hard error occurs in the memory cell array in a case where the first ECC circuit is unable to correct the error. In a case where the hard error occurs, the second ECC circuit performs error correction using second read data that excludes a bit where the hard error occurs.Type: ApplicationFiled: August 22, 2018Publication date: September 19, 2019Inventor: Eietsu TAKAHASHI
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Publication number: 20190108885Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: December 4, 2018Publication date: April 11, 2019Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Publication number: 20190088331Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.Type: ApplicationFiled: March 9, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Takashi Kobayashi, Yoichi Minemura, Eietsu Takahashi, Masaki Kondo, Daisuke Hagishima
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Patent number: 10186321Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: March 8, 2018Date of Patent: January 22, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20180308550Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: ApplicationFiled: July 2, 2018Publication date: October 25, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI
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Patent number: 10043579Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: GrantFiled: September 15, 2017Date of Patent: August 7, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi
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Publication number: 20180197616Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Patent number: 9947415Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: May 18, 2017Date of Patent: April 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Patent number: 9928915Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.Type: GrantFiled: October 21, 2016Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
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Publication number: 20180005695Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: ApplicationFiled: September 15, 2017Publication date: January 4, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI
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Patent number: 9805798Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: GrantFiled: November 8, 2016Date of Patent: October 31, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi
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Publication number: 20170256321Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Patent number: 9691489Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: September 13, 2016Date of Patent: June 27, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Patent number: 9672926Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage (first threshold voltage<second threshold voltage), and the control circuit changes a charge voltage for the bit lines between the first verify operation and the second verify operation.Type: GrantFiled: August 29, 2013Date of Patent: June 6, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Nobushi Matsuura, Masashi Yoshida, Eietsu Takahashi
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Patent number: 9627087Abstract: According to one embodiment, a memory device includes a string unit including a plurality of memory cell transistors which are connected in series, a first select transistor connected to a first end of the plurality of memory cell transistors, and a second select transistor connected to a second end of the plurality of memory cell transistors; and a bit line connected to the first select transistor.Type: GrantFiled: March 9, 2016Date of Patent: April 18, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Koji Kato, Eietsu Takahashi