Patents by Inventor Eiji Miyamoto
Eiji Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7256558Abstract: A brushless motor according to the present invention provided with a recording disk in a rotational member and serving to rotate the recording disk together with the rotational member comprises a first position detecting means for detecting a rotational position of the rotational member, a second position detecting means for detecting a rotational position of the recording disk, wherein a mode for rotating the rotational member at a high speed by a detection signal of the first position detecting means and a mode for rotating the rotational member at a low speed by a detection signal of the second position detecting means are generated. Thereby, the two rotation states whose rotation speeds are different can be obtained in a simplified constitution.Type: GrantFiled: August 2, 2005Date of Patent: August 14, 2007Assignee: Nidec CorporationInventors: Naoki Mine, Eiji Miyamoto
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Publication number: 20070128089Abstract: A particulate matter-removing filter being resistant to clogging and ash blocking, requiring no special means such as back-washing and heating combustion, and being formed of inexpensive materials; and exhaust emission controlling method and device using this. (1) A particulate-matter-containing exhaust emission controlling filter which uses as a basic unit a pair of porous corrugated sheet and a porous flat sheet that support an exhaust emission controlling catalyst, has a molding formed by laminating the porous corrugated sheets so that their ridge lines alternately cross perpendicularly, has one of side surfaces, perpendicularly crossing the corrugated sheet ridge lines, of the molding or mutually-adjoining two surfaces that are the perpendicularly-crossing side surfaces sealed, and has exhaust gas in-flow passage and out-flow passage respectively formed between porous corrugated sheets via a porous flat sheet.Type: ApplicationFiled: November 24, 2004Publication date: June 7, 2007Inventors: Yasuyoshi Kato, Takashi Michimoto, Eiji Miyamoto, Naomi Imada, Masatochi Fujisawa, Kazuki Kobayashi, Hiroshi Ishizaka, Takeshi Hirota
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Publication number: 20070123041Abstract: [PROBLEM TO BE SOLVED]In a surface processing apparatus for spraying a processing gas onto the surface of an object to be processed through a hole-row such as a slit, the surface of the object having a large area can effectively be processed even if the hole-row is short. [MEANS FOR SOLVING] A plurality of electrode plates 11, 12 are arranged, in side-by-side relation, on a processor 1 of a plasma surface processing apparatus M. A slit-like hole-row 10a is formed between the adjacent electrode plates, and a hole-row group 100 is constituted by the side-by-side arranged hole-rows 10a. The object W is moved along the extending direction of each slit 10a by a moving mechanism 4.Type: ApplicationFiled: June 24, 2004Publication date: May 31, 2007Applicant: SEKISUI CHEMICAL CO., LTD.Inventors: Junichiro Anzai, Yoshinori Nakano, Shinichi Kawasaki, Sumio Nakatake, Satoshi Mayumi, Eiji Miyamoto, Toshimasa Takeuchi
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Patent number: 7203101Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: GrantFiled: January 12, 2006Date of Patent: April 10, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20060284497Abstract: A magnet disposed on the top face of an extended part of a bearing holding member has a semicircle shape as the maximum shaper and is disposed in the same direction as the movement direction of a disk dray in the circumferential direction. By the pulling force in the axial direction between the magnet and a rotor holder, the shaft tilts at an angle different from the gravity direction or a direction opposite to the gravity direction.Type: ApplicationFiled: June 20, 2006Publication date: December 21, 2006Applicant: NIDEC CORPORATIONInventors: Hitoshi Takaki, Hisakazu Motomochi, Eiji Miyamoto, Takuya Yamane
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Publication number: 20060260748Abstract: A nozzle head NH of a plasma processing apparatus comprises an annular inner holder 3, an annular inner electrode 11 surrounding this holder 3, an annular outer electrode 21 surrounding this electrode 11, and an annular outer holder 4 surrounding this electrode 21. The inner holder 3 is provided with a plurality of bolts 7 spacedly arranged in the peripheral direction and adapted to push the inner electrode 11 radially outwardly. The outer holder 4 is provided with a plurality of bolts 8 spacedly arranged in the peripheral direction and adapted to push the outer electrode 21 radially inwardly. Owing to this arrangement, the operation for disassembling, assembling and centering the annular electrodes 11, 21 can be carried out with ease.Type: ApplicationFiled: March 4, 2004Publication date: November 23, 2006Inventors: Mitsuhide Nogami, Eiji Miyamoto
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Publication number: 20060120125Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: ApplicationFiled: January 12, 2006Publication date: June 8, 2006Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7016236Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: GrantFiled: April 8, 2005Date of Patent: March 21, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20060022621Abstract: A brushless motor according to the present invention provided with a recording disk in a rotational member and serving to rotate the recording disk together with the rotational member comprises a first position detecting means for detecting a rotational position of the rotational member, a second position detecting means for detecting a rotational position of the recording disk, wherein a mode for rotating the rotational member at a high speed by a detection signal of the first position detecting means and a mode for rotating the rotational member at a low speed by a detection signal of the second position detecting means are generated. Thereby, the two rotation states whose rotation speeds are different can be obtained in a simplified constitution.Type: ApplicationFiled: August 2, 2005Publication date: February 2, 2006Inventors: Naoki Mine, Eiji Miyamoto
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Publication number: 20050179058Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: ApplicationFiled: April 8, 2005Publication date: August 18, 2005Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 6898130Abstract: A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: GrantFiled: October 14, 2003Date of Patent: May 24, 2005Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20040256926Abstract: A brushless motor includes a rotor position detecting device disposed between stator teeth, rather than directly below a rotor magnet, so that the distance between a lower end of a rotor magnet and a stationary frame is minimized. This results in a thinner brushless motor than conventional designs. In the preferred embodiment of the present invention, the rotor position detecting device is a Hall device.Type: ApplicationFiled: July 16, 2004Publication date: December 23, 2004Applicant: Nidec CorporationInventor: Eiji Miyamoto
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Patent number: 6833117Abstract: The catalyst structure of the present invention for purifying an exhaust gas is preferable for increasing the contact of an exhaust gas, to be treated, with a catalyst by disturbing the flow of the exhaust gas in a gas flow passage thereby obtain a highly efficient and compact apparatus for treating the exhaust gas. Such catalyst structure is produced by forming two or more catalyst elements each supporting a catalyst component on its surface and having flat plate portions and level-changing portions formed alternately therein with the angle formed between the flat plate portion and the level-changing portion being in a specific range, and then stacking the catalyst elements in a frame. A catalyst structure is also obtained by stacking a large number of the catalyst elements described above through metallic, ceramic, or glass netlike members interposed therebetween and each having a large number of perforated holes.Type: GrantFiled: June 14, 2000Date of Patent: December 21, 2004Assignee: Babcock-Hitachi Kabushiki KaishaInventors: Yasuyoshi Kato, Yoshinori Nagai, Kouichi Yokoyama, Naomi Yoshida, Takashi Michimoto, Eiji Miyamoto, Masatoshi Fujisawa
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Publication number: 20040240259Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: ApplicationFiled: October 14, 2003Publication date: December 2, 2004Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 6806601Abstract: A brushless motor includes a rotor position detecting device disposed between stator teeth, rather than directly below a rotor magnet, so that the distance between a lower end of a rotor magnet and a stationary frame is minimized. This results in a thinner brushless motor than conventional designs. In the preferred embodiment of the present invention, the rotor position detecting device is a Hall device.Type: GrantFiled: March 10, 2003Date of Patent: October 19, 2004Assignee: Nidec CorporationInventor: Eiji Miyamoto
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Patent number: 6710013Abstract: Provided is a catalyst structure used for purifying an exhaust gas; to be disposed in an exhaust gas flow passage; preferable for obtaining a highly efficient and compact exhaust gas purifying apparatus; and produced by alternately stacking platelike catalysts 1, and gas dispersing members composed of netlike products 7 having many holes passing from the front surface to the back surface thereof, or linear, belt-shaped, or rodlike materials of a metal, ceramic, or glass to disturb the flow of an exhaust gas in a flow passage of the gas thereby to promote contact of the gas to be treated with the catalyst.Type: GrantFiled: April 20, 2001Date of Patent: March 23, 2004Assignee: Babcock-Hitachi Kabushiki KaishaInventors: Yasuyoshi Kato, Kouichi Yokoyama, Eiji Miyamoto, Masatoshi Fujisawa
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Patent number: 6657901Abstract: A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: GrantFiled: September 26, 2002Date of Patent: December 2, 2003Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20030178904Abstract: A brushless motor includes a rotor position detecting device disposed between stator teeth, rather than directly below a rotor magnet, so that the distance between a lower end of a rotor magnet and a stationary frame is minimized. This results in a thinner brushless motor than conventional designs. In the preferred embodiment of the present invention, the rotor position detecting device is a Hall device.Type: ApplicationFiled: March 10, 2003Publication date: September 25, 2003Applicant: Nidec CorporationInventor: Eiji Miyamoto
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Publication number: 20030031058Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: ApplicationFiled: September 26, 2002Publication date: February 13, 2003Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 6515913Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: GrantFiled: December 4, 2001Date of Patent: February 4, 2003Assignee: Hitachi, Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata