Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A storage media driving motor having a shaft, a turntable jointly rotatable with a replaceable storage media mounted on the shaft, a rotor yoke rotating jointly with the turntable, a stator including a core and a winding wound around the core, and a driving magnet fitted into the rotor yoke so as to oppose the stator. The turntable and the rotor yoke are integrally formed so as to define a rotor, and inner-periphery-side concave section opening outwardly in the axial-line direction of the rotor formed in the vicinity of a portion where the rotor is fitted to the shaft, and a center ring for determining the position of the storage media is arranged in the inner-periphery-side concave section.

Abstract: The present invention discloses a disk drive motor comprising a rotor having an annular space formed therein coaxially with the axis of rotation, and balancing member accommodated in the annular space and capable of changing its mass distribution circumferentially along the circle of the annular space. In case of any imbalanced rotation occurring during the rotation, the balancing member temporarily gather to a portion of the annular space where the mass imbalance is taking place. However, when the motor speed exceeds the value at which resonance takes place due to coincidence between the frequency of the vibration of the balancing member and the natural frequency of the motor, the balancing members move to a position symmetrical with the point of mass imbalance to eliminate the mass imbalance, thereby suppressing the run-out.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: The present invention discloses a disk drive motor comprising a rotor having an annular space formed therein coaxially with the axis of rotation, and balancing member accommodated in the annular space and capable of changing its mass distribution circumferentially along the circle of the annular space. In case of any imbalanced rotation occurring during the rotation, the balancing member temporarily gather to a portion of the annular space where the mass imbalance is taking place. However, when the motor speed exceeds the value at which resonance takes place due to coincidence between the frequency of the vibration of the balancing member and the natural frequency of the motor, the balancing members move to a position symmetrical with the point of mass imbalance to eliminate the mass imbalance, thereby suppressing the run-out.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A weft knitted composite fabric comprises a frontal layer of a weft knitted fabric, a rear layer of a weft knitted fabric and binding yarns. Said rear layer of the weft knitted fabric is bound with said frontal layer by weave of said binding yarns and arranged with a given distance separating the frontal layer and the rear layer. Said binding yarns are more stiff than knitting yarns of said frontal layer and said rear layer. Said binding yarns comprise S-twist yarns and Z-twist yarns alternately. Said frontal layer of a weft knitted fabric may include knitting yarns for pile so that a surface of said frontal layer is provided with a pile.

Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal.

Abstract: A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

Abstract: A magnet pump in which an impeller having a permanent magnet embedded therein is rotatably driven by a magnetic force from the outside of the impeller is disclosed. The pump comprises a pump casing including a suction port, a discharge port and a pumping chamber in which the impeller is contained. The impeller is rotatably contained in the pumping chamber of the casing and has the permanent magnet embedded therein. A pair of bearings, one being fixed to the casing and the other being fixed to the impeller is provided. A magnetic force driving mechanism constitutes a means for affording the magnetic force on the permanent magnet within the impeller to rotatably drive the latter. The magnetic force driving mechanism is mounted on a non-liquid-contacting portion of the casing at a position facing the impeller in respect to the direction of the rotary shaft axis of the impeller.

Abstract: A substrate back bias voltage generator of a dynamic type RAM is provided with a first voltage generator having a relatively large current supply capacity, a second voltage generator having a relatively small current supply capacity, and a substrate back bias voltage detecting circuit for controlling operation of the first voltage generator. For example, when the dynamic type RAM is in a CAS before RAS refresh mode, the operation of the first voltage generator is limited selectively, and the operation of the second voltage generator and the substrate back bias voltage detecting circuit is stopped selectively.

Abstract: Back-splitting apparatus for use in the production of books such as account books, notebooks, textbooks and the like for separating a block of stacked sheets of paper, bound together at one side by gluing and constituting a plurality of books, into individual books. A plurality of projection pieces are provided at one sides of the final sheets of the respective books of the block. A suction member is disposed at the position faced with one of the projection pieces, and a pawl member is disposed movably to the lower portion of the suction member. The block of stacked sheets of paper is separated into individual books accurately by advancing a back-splitting cutter knife into the back surface side of the projection piece interposed between the suction member and the pawl member. Thus, this apparatus can effectively separate a block of stacked sheets of paper made of thick and extremely thin sheets.

Abstract: A cutter for a cutting machine wherein a large number of inclined grooves having an angle relative to the edge of the cutter are formed in parallel on the rear side of the cutter, whereby the job of cutting stacked sheets of paper into book blocks of a predetermined size and the job of forming groove portions at the back parts of the book blocks can be simultaneously executed in the production of brochures.