Abstract: The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis. The conversion system may also include the use of a backup conversion path for use when the main conversion path overranges. The backup conversion path may utilize a dedicated backup converter.

Abstract: A successive approximation ADC is provided. Contacts to a resistor string may be placed outside of the current path of the resistor string to provide a highly stable resistor string having a very low temperature drift. The resistor string may be utilized to calibrate a successive approximation ADC. The resistor string may also be a portion of a resistor array of a resistor and capacitor array ADC. The resistor string may be calibrated with a calibration ADC having a resolution greater than the resistor string. The calibration ADC may be a delta sigma ADC.

Abstract: In a signal processing integrated circuit having a plurality of physical channels and a plurality of gain registers, a plurality of offset registers and an plurality of setup registers, mechanisms are provided to assign one of a plurality of gain registers independently of a selected one of a plurality of offset registers when processing signals from a physical channel.

Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.

Abstract: Techniques are disclosed for permitting low power operation of a signal processing circuit, such as a mixed signal processing circuit, by operating devices of the digital signal processing side at an energy-delay minimum. To permit this to occur, the negative logic supply rail of the digital signal processing circuit is operated at a negative potential. This negative potential is generated using a charge pump on an integrated circuit chip which can be also used to create a negative substrate potential. A positive logic supply rail can be generated using a DC to DC converter or voltage regulator. The potential of the positive logic supply rail can be negative, as long at it is more positive than the potential of the negative logic supply rail.

Abstract: A programmable gain preamplifier is provided which has a low temperature drift and good dynamic range characteristics. The programmable gain preamplifier may be coupled to an analog to digital converter. The analog to digital converter may be a switched capacitor array analog to digital converter. The analog to digital converter may be a resistor array and capacitor array analog to digital converter. A resistor string having contacts out of the resistor string current path may be utilized with the programmable gain preamplifier or the analog to digital converter or both. The resistor string may be utilized to calibrate the analog to digital converter or the programmable gain preamplifier or both. The resistor string may also be utilized by the analog to digital converter when conversions are being performed. The programmable gain preamplifier provides a programmable gain of the difference between two input signals (Ain and Ain′ for example).

Abstract: A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324) This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332) Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.

Abstract: A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.

Abstract: A system and method is provided for providing optimal input and output impedances at a telecommunications interface. Input and output impedances can be adjusted manually, or the optimal impedance can be sensed and provided for automatically at the selected interface.

Abstract: A programmable gain preamplifier is provided which has a low temperature drift and good dynamic range characteristics. The programmable gain preamplifier provides a programmable gain of the difference between two input signals (Ain and Ain′ for example). One of the input signals (Ain′) may be an estimation of the other input signal (Ain). The estimation input signal (or a signal related to the estimated input) may be generated by the use of a reference voltage and a first resistor string. More particularly, the reference voltage and the first resistor string may operate as a digital to analog converter (DAC) that converts a digital estimation signal to an analog estimation voltage. The analog estimation voltage operates as an analog voltage that is a function of (or the same as) the analog Ain′ estimation signal. The first resistor string may provide the estimation voltage without loading the resistor string.

Abstract: A technique for detecting error when transferring data on a data channel between components disposed on the data channel. A test pattern is generated by a controller on the data channel and sent to a data storage component on the channel. The data storage component tests the received test pattern to determine if the pattern has been corrupted.

Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.

Abstract: A gain ranging AD converter is provided having two separate gain paths. There is provided a low-gain path and a high-gain path. The low gain path is processed through an analog modulator (333) and then through a filter section to provide on an output of a high-pass filter (339), a low-gain signal which is then compensated for in an equalizer section (347). This equalizing section (347) calibrates the output signal to ensure that the difference between the calibrated signal and the high-gain signal differs only by the fixed gain between the two paths. The high-gain path also includes a modulator (335) for processing through a filter section to provide on the output of a high-pass filter section (343) a high-gain signal. A calibration generator (361) is utilized to generate the parameters for performing the equalization.

Abstract: A technique for reducing jitter on a data channel utilized for transfer of data between components disposed on the channel. Instead of coupling a ground of the channel directly to a ground network of a chip containing the data transferring device, an impedance between the channel ground and a substrate is utilized to minimize the jitter.

Abstract: A linear phase FIR filter includes a multiplication/accumulator engine which is operable to receive the multi-level data stream and multiply it by predetermined filter coefficients. The coefficients are symmetrical to allow a pre-addition operation wherein the data is first stored in a buffer and then the data for symmetrical coefficients added before multiplication by the coefficient. This results in a reduction of multiplications by a factor of two, thus allowing the multiplication/accumulator engine to operate at one-half the clock rate of the oversampled multi-level data bit stream.

Abstract: An analog modulator is provided having seven switched-capacitor integrators (62)-(74) disposed in a leap-frog filter configuration with a plurality of feedback taps (76)-(88) provided from the output to each of the integrators (62)-(74). These are summed in a summation junction (90), the output thereof input to a quantizing circuit (92) for input back to a summation junction alter a D to A circuit (60) for summation with the analog input signal and then input to the first integrator (62). The first feedback structures (98)-(102) are provided for connection between the output of the last of the integrated structures (74) and the input of the preceding one thereof such that the feedback structure (98) is connected across integrators (64) and integrator (66), feedback structure (100) connected between integrators (68)-(70) and integrator (102) connected against integrators (72) and (74).

Abstract: An analog-to-digital converter is comprised of an analog delta-sigma modulator (10) and a digital processing section (14). The digital processing section (14) is comprised of a plurality of digital processing sections fabricated on a monolithic device. A high precision FIR filter (20) is provided for providing a high resolution output on a bus (22). Additionally, a low group delay FIR filter (30) is provided to filter the data and provide an output with a much lower delay than that of the FIR filter (20). The output of filter (20) can either be processed through a high-pass filter (40) and/or through a noise shaping psycho-acoustic filter (36) to provide select outputs. These outputs are all input to the serial interface device (52), which is operable to select one of the outputs, that of the filter (30), that of the filter (20), or that of the output of the noise shaping filter (36) or that of the filter (40) for conversion to a serial data stream.

Abstract: The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.

Abstract: A differential input stage for a data conversion device includes two sections, one section for operating during a high stress portion of a charge transfer operation and one portion for operating during the remainder of the charge transfer operation. The first portion is comprised of two differential transistors (84) and (86) having the sources and bodies thereof connected to a source coupled node and connected through a switch (94) to a current source (92). The drains of transistors (84) and (86) are connected through switches (110) and (112), respectively, to output terminals. During the second half of the charge transfer operation, differential transistors (78) and (88), having the sources and bodies thereof connected to a source coupled node and connected to the current source (92) through a switch (90), are rendered operable with the drains thereof connected through switches (96) and (104), respectively, to the output terminals. Only one of the differential pairs is operable at any one time.