Abstract: A non-volatile memo includes the reference cells programmed to opposite logic states whose outputs are combined and then equally divided to provide a reference signal to a sense amplifier which is one half of the sum of the signals from a high conductivity data cell and a low conductivity data cell. The non-volatile memory also includes a bias voltage generator which uses a high conductivity non-volatile reference cell for a reference, and which produces a bias voltage which is coupled to current limiting transistors at the inputs of the sense amplifier so that the current into the sense amplifier is limited and therefore limits the power used by the non-volatile memory.

Abstract: Abnormal changes in the non-linear characteristics of electronic components are an indication of abnormal conditions such as impending component or system failure. To detect such abnormal changes in nonlinearity, an electronic circuit is subjected to a calibration signal including at least one frequency component. Nonlinearity in the electronic circuit causes distortion components to be generated from the calibration signal. Preferably the nonlinearity is characterized by compensation coefficients that digitally compensate the nonlinearity. The compensation coefficients are adjusted in a feedback loop in response to measured values of the distortion components, so that the distortion components are minimized. At the end of the adjustment process, the transfer function of the electronic circuit is specified by the compensation coefficients, which are stored in memory.

Abstract: The output gates of a delta-sigma modulator can generate i(t) transient signal in the power supply lines of a delta-sigma modulator. These i(t) spikes, which would otherwise produce non-linearities which can be coupled into the frequency band of interest of the modulator, are made to be linear by using return-to-zero data encoding and by providing multi-bit outputs to the delta-sigma modulator in which the output states all have equal numbers of logic ones at the output lines for each of the output states.

Abstract: A method and apparatus for calibration of errors in a monolithic reference includes a bandgap voltage reference (50) that outputs an untrimmed voltage and a temperature voltage. The untrimmed voltage and temperature voltage are input to a delta-sigma A/D converter (52) which has the output thereof processed through a digital filter (54) to output data on a data bus (58) for storage in an EEPROM (60). The EEPROM (60) is operable in one mode to store temperature history data and, in another mode, to store temperature compensation data. In one mode, temperature compensation parameters are retrieved from the EEPROM (60) and utilized by a multiplier/accumulator circuit (74) to generate compensation factors which are output as a digital word to a DAC (76) for controlling a trim circuit (14). The trim circuit (14) provides a temperature compensation for the output of the bandgap voltage reference (50).

Abstract: The thermal noise generated through the feedback capacitor of a delta-sigma modulator is attenuated by transferring a reference voltage through the capacitor in two separate steps during each sampling period. This permits a reduction in the size of the feedback capacitor, thereby reducing thermal noise, without increasing the voltage on the switching capacitors on the summing node side of the feedback capacitors which would induce degradation due to hot electron effects.

Abstract: A method and apparatus for calibration of errors in the analog reference voltage input of an analog-to-digital converter. A monolithic reference voltage generator is provided to generate the analog reference which includes a bandgap voltage reference (50) that outputs an untrimmed voltage and a temperature voltage. The untrimmed voltage and temperature voltage are input to a delta-sigma A/D converter (52) which has the output thereof processed through a digital filter (54) to output data on a data bus (58) for storage in an EEPROM (60). The EEPROM (60) is operable in one mode to store temperature history data and, in another mode, to store temperature compensation data. In one mode, temperature compensation parameters are retrieved from the EEPROM (60) and utilized by a multiplier/accumulator circuit (74) to generate compensation factors which are output as a digital word to a DAC (76) for controlling a trim circuit (14).

Abstract: A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta.

Abstract: Method and circuitry for decreasing the recovery time of an MOS differential voltage comparator after an input voltage overdrive. At the beginning of a comparison cycle a reverse voltage is momentarily applied between the gates and sources of the input pair of source-coupled MOS transistors of sufficient magnitude to form a charge accumulation layer in the channel region of each of the transistors. Operating the differential voltage comparator in such manner substantially decreases the time required for the transistors to recover from an imbalance in their electrical characteristics caused by the input voltage overdrive.

Abstract: An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.

Abstract: An amplifier with controlled output impedance has a first output connected to the inverting input of the amplifier, and a second output, which forms the output of the amplifier, connected through a feedback conductance to the inverting input of the amplifier. A input conductance is connected from the inverting input to ground, and the input signal is connected to the positive input of the amplifier. The first and second outputs are provided by first and second current output stages. The currents provided by the first and second output stages are proportional to each other by a predetermined ratio. By proper selection of this predetermined ratio and the feedback and input conductances the desired output impedance and overall gain of the amplifier into a given load can be achieved.

Abstract: An optical communication system includes two optical modems (12) and (14) which are disposed at either end of an optical fiber data link (10). The optical modems (12) and (14) communicate through LEDs (16) and (18), respectively, with the fiber data link (10). Each of the optical modems (12) and (14) on start-up are peerless and do not operate in either a master or a slave configuration. A ping-pong transmission format is utilized with transmitted packets of data. When one of the optical modems (12) or (14) detects a transmitted packet from the other, it locks up to the transmitted packet with a phase lock loop and takes on slave status. This slave status is transmitted back to the fiber data link (10) in another transmitted packet. The transmitted packet from the slave device is then adjusted time relative to the machine cycle of the slave device until the packet is received by the other optical modem.

Abstract: A calibration circuit for a linear channel of an optical modem includes circuitry interconnected to the linear channel for causing the linear channel to oscillate. Circuitry is interconnected to the output of the linear channel for monitoring the bandwidth of the linear channel during oscillation and for generating output pulses. The output pulses are counted and are utilized for generating an adjustment signal applied to the linear channel for adjusting the bandwidth of the linear channel.

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which is a single-ended integrator. The second, third, and fourth integrator stages are fully-differential integrators. The first integrator provides the required thermal noise characteristics of the loop filter with only one feedback capacitor which is external to the integrated circuit chip, while the fully-differential integrator stages provide improved suppression of charge injection transients.

Abstract: A phase equalization system for a digital-to-analog converter (DAC) includes a digital portion (10) having an interpolation section (14) for receiving a digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modudlator (16) to allow an offset voltage to be summed therewith. This provides for D.C. offset, this offset being controlled by a calibration control (40). The output of the digital section (10) is input in an analog section (12), which has a one-bit DAC 21) that is input to an analog filter (22) for converting and filtering the one-bit digital stream output by the delta-sigma modulator (16). The interpolation circuit (14) includes a three stage interpolation filter comprising a first stage (50), a second stage (52) and a third stage (54). The second stage (52) is comprised of a finite impulse response filter (FIR) that has a nonlinear phase response.

Abstract: An oscillation detect and reset circuit is provided for an analog modulator that includes a first stage of integration having a single ended differential amplifier (32) which is connected to the input of three stages of subsequent integration (40), (42) and (44), in a cascaded configuration. The output of the last stage of integration (44) is connected to the input of a one-bit quantizer (48). The output of the one-bit quantizer (48) is connected to the input of a current (50) feedback, which is connected between a summing node (36) and a negative voltage supply. The summing node (36) sums the current feedback with an input voltage for input to the amplifier (32). Switches (52), (54) and (56) are provided across the inputs and outputs of the integration stages (40), (42) and (44), respectively. The sensing of an unstable condition on the output of second stage of integration (40) is detected by oscillation detect comparators (60) and (62) to initiate a count cycle in a five-bit counter (66).

Abstract: A method and circuitry for time-sharing a digitally-programmable capacitive element, particularly in conjunction with a switched-capacitor filter circuit. The method includes: selecting a first capacitance value for the capacitive element; initializing the charge on the capacitive element; connecting the capacitive element to first preselected nodes of an electronic circuit; disconnecting the capacitive element from the first preselected nodes of after any charge transfer has substantially been completed; changing the capacitance of the capacitive element to a new desired value; initializing the charge on the capacitive element; and then connecting the capacitive element to other preselected nodes of the electronic circuit. A biquad switched-capacitor filter circuit is configured to use such method in its operation.

Abstract: Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.

Abstract: An MOS current mirror arrangement is disclosed wherein selected ones of the input and output transistors are designed to have a threshold voltage, V.sub.T1, greater in magnitude that associated with standard MOS devices. The larger threshold voltage thus eases the requirement that the turn-on voltage, V.sub.ON, remain less than the threshold voltage V.sub.T, for the devices to remain in the active region of operation. Since a minimum value of V.sub.T is useful for some applications (fast processing and operation at high temperatures) the use of mixed thresholds allows both requirements to be met by adjusting the thresholds of selected devices associated with these different requirements. The difference in threshold voltages can be attained simply by adjusting the threshold adjust implant mask to protect selected devices from the ion implantation conventionally used to decrease the magnitude of the threshold voltage.

Abstract: The present invention relates to a floating input comparator capable of mitigating the effects of parasitic capacitance present at the input stage of the comparator. In particular, the present invention functions to substantially reduce the effects of parasitic capacitive voltage division present at the nodes interrogated during each detection cycle. In accordance with the present invention, precharging devices (40, 42, 44) are coupled between a predetermined reference potential (VDD) and the affected nodes (D, E, C) to precharge the nodes to the full reference potential prior to each detection cycle, thereby eliminating the effects of a changing, unknown parasitic capacitance at these nodes by replacing an unknown parasitic potential with the known reference potential.