Abstract: An electronic sample-and-hold circuit (10, 24) of the type which includes a correction network is designed to eliminate a primary signal feedback loop. A correction capacitor, (C.sub.C), a coupling capacitor (C.sub.CC), and a primary holding capacitor (C.sub.H) are connected in series, respectively, between two ground points. The common node of the coupling capacitor and the holding capacitor is a held signal node (12). The common node of the coupling capacitor (C.sub.CC) and the correction capacitor (C.sub.C) is a correction voltage node (20). The circuit output is from the signal node (12) through a buffer (14) and a stage selecting switch (S.sub.F). The output is fed back to an operational amplifier (18, 26) which has its output connected to the correction node (20) through a correction sampling switch (S.sub.C). A switched (S.sub.A) feedback loop connects the output of the amplifier 18 to the inverting input port.

Abstract: The feedback sample-and-hold stages of a transversal filter bank include a primary sample-and-hold branch and a secondary sample-and-hold branch for correction of offset voltage in the primary branch which results from switching charge feedthrough of its sampling switch. A pair of N-channel buffer transistors, one an enhancement type and one a depletion type, are so connected to the branches that power supply noise is attenuated. Additionally, the parasitic capacitance of the enhancement transistor acts as a coupling capacitor for the correction function.

Abstract: An enhancement mode (104, 204, 404) and a depletion mode (102, 202, 402) pair of N-channel MOS transistors have their drain-source conduction paths connected in series and provided with a bias current means (120, 220, 306, 410). The gates (106, 206, 308, 310) are coupled together as an input node. In one embodiment (100) their bulk regions are source-connected and the output (118) is from the source of the enhancement mode device (104) to obtain a source follower configuration amplifier. In a second embodiment (200), the output (218) is taken from the drain (208) of the depletion mode device (202) to obtain a common source configuration amplifier. Two source follower pairs (302, 304) are disclosed connected in parallel to form a differential input voltage amplifier stage (300). A common source pair (402, 404) is disclosed in combination with an additional enhancement mode transistor (406) to form a current mirror (400).

Abstract: Two gate-coupled pairs (12, 14; 16, 18) of MOS transistors are configured in a compound current mirror (10, 30) arrangement. Each pair includes an input (12; 16) and an output (14; 18) transistor. The output transistors are connected with their conduction paths in series between a source of output current a reference voltage node (22). Each of the input transistors is connected with its conduction path between the reference voltage node (22) and a separate current source (20, 24), with both sources supplying the same input current. One of the input transistors (12, 60) has a conduction path width-to-length ratio which is one-fourth that of the other one (16). This makes it possible to bias the output transistors with the minimum ON voltage for operation in the active region and thereby reduces power supply voltage overhead.