Patents by Inventor Eric S. Shapiro
Eric S. Shapiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11190183Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.Type: GrantFiled: August 10, 2020Date of Patent: November 30, 2021Assignee: pSemi CorporationInventors: Eric S. Shapiro, Payman Shanjani
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Patent number: 11075612Abstract: A phase shifter unit cell or a connected set of such cells that can be well isolated from external circuitry and which do not introduce insertion loss into an RF signal path, exhibit good return loss, and further provides additional advantages when combined with bracketing attenuator circuits. More particularly, embodiments integrate a high-isolation function within a phase shifter circuit by breaking the complimentary nature of the control signals to a phase shifter cell to provide greater control of switch states internal to the phase shifter cell and thus enable a distinct high-isolation state, and by including a switchable shunt termination resistor for use in the high-isolation state. Some embodiments are serially coupled to attenuator circuits to enable synergistic interaction that reduces overall die size and/or increases isolation. One such embodiment positions a high-isolation phase shifter cell in accordance with the present invention between bracketing programmable attenuators.Type: GrantFiled: June 5, 2020Date of Patent: July 27, 2021Assignee: pSemi CorporationInventors: Eric S. Shapiro, Peter Bacon
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Patent number: 11049855Abstract: Overcoming parasitic capacitances in RF integrated circuits is a challenging problem. The disclosed methods and devices provide solution to such challenge. Devices based on tunable capacitive elements that can be implemented with switch RF stacks are also disclosed.Type: GrantFiled: August 9, 2018Date of Patent: June 29, 2021Assignee: pSemi CorporationInventors: Eric S. Shapiro, Simon Edward Willard, Tero Tapio Ranta
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Publication number: 20210143809Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained.Type: ApplicationFiled: November 18, 2020Publication date: May 13, 2021Inventors: Payman Shanjani, Eric S. Shapiro
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Patent number: 10942212Abstract: Systems and methods for testing radio frequency FET switches at high RF voltages. Embodiments utilize an impedance transformer, or resonator, to step up the available voltage from an RF signal generator and amplifier to a device under test (DUT). The resonator reduces the RF power required to test at higher voltages, resulting in lower cost and other benefits. When a DUT begins to exhibit excessive non-linear distortion, resonance is lost, applied RF test signal power is reflected back as a reflected signal, and current to the DUT is starved by the resonator, protecting the DUT from destructive power levels. Measuring the amplitude of the reflected signal at the harmonic frequencies of the RF test signal allows detection of a harmonic knee point for selected reflected signal harmonics, and consequently allows determination of the power level of the RF test signal at which excessive non-linear distortion occurs.Type: GrantFiled: December 5, 2018Date of Patent: March 9, 2021Assignee: pSemi CorporationInventors: Eric S. Shapiro, Tero Tapio Ranta, William Joseph Jasper
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Publication number: 20210028783Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.Type: ApplicationFiled: August 10, 2020Publication date: January 28, 2021Inventors: Eric S. Shapiro, Payman Shanjani
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Publication number: 20210013841Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.Type: ApplicationFiled: July 22, 2020Publication date: January 14, 2021Inventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
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Patent number: 10884050Abstract: A stack of series coupled transistors comprising, at least two sub-portions of the stack of series coupled transistors, and at least one logic decoder coupled to the at least two sub-portions to turn ON at least one sub-portion.Type: GrantFiled: June 21, 2016Date of Patent: January 5, 2021Assignee: pSemi CorporationInventor: Eric S. Shapiro
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Publication number: 20200373898Abstract: A phase shifter unit cell or a connected set of such cells that can be well isolated from external circuitry and which do not introduce insertion loss into an RF signal path, exhibit good return loss, and further provides additional advantages when combined with bracketing attenuator circuits. More particularly, embodiments integrate a high-isolation function within a phase shifter circuit by breaking the complimentary nature of the control signals to a phase shifter cell to provide greater control of switch states internal to the phase shifter cell and thus enable a distinct high-isolation state, and by including a switchable shunt termination resistor for use in the high-isolation state. Some embodiments are serially coupled to attenuator circuits to enable synergistic interaction that reduces overall die size and/or increases isolation. One such embodiment positions a high-isolation phase shifter cell in accordance with the present invention between bracketing programmable attenuators.Type: ApplicationFiled: June 5, 2020Publication date: November 26, 2020Inventors: Eric S. Shapiro, Peter Bacon
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Patent number: 10848141Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.Type: GrantFiled: August 12, 2019Date of Patent: November 24, 2020Assignee: pSemi CorporationInventors: Payman Shanjani, Eric S. Shapiro
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Patent number: 10771059Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.Type: GrantFiled: January 3, 2019Date of Patent: September 8, 2020Assignee: pSemi CorporationInventors: Eric S. Shapiro, Payman Shanjani
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Patent number: 10756678Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.Type: GrantFiled: January 17, 2019Date of Patent: August 25, 2020Assignee: pSemi CorporationInventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
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Patent number: 10693435Abstract: A phase shifter unit cell or a connected set of such cells that can be well isolated from external circuitry and which do not introduce insertion loss into an RF signal path, exhibit good return loss, and further provides additional advantages when combined with bracketing attenuator circuits. More particularly, embodiments integrate a high-isolation function within a phase shifter circuit by breaking the complimentary nature of the control signals to a phase shifter cell to provide greater control of switch states internal to the phase shifter cell and thus enable a distinct high-isolation state, and by including a switchable shunt termination resistor for use in the high-isolation state. Some embodiments are serially coupled to attenuator circuits to enable synergistic interaction that reduces overall die size and/or increases isolation. One such embodiment positions a high-isolation phase shifter cell in accordance with the present invention between bracketing programmable attenuators.Type: GrantFiled: October 31, 2018Date of Patent: June 23, 2020Assignee: pSemi CorporationInventors: Eric S. Shapiro, Peter Bacon
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Publication number: 20200182924Abstract: Systems and methods for testing radio frequency FET switches at high RF voltages. Embodiments utilize an impedance transformer, or resonator, to step up the available voltage from an RF signal generator and amplifier to a device under test (DUT). The resonator reduces the RF power required to test at higher voltages, resulting in lower cost and other benefits. When a DUT begins to exhibit excessive non-linear distortion, resonance is lost, applied RF test signal power is reflected back as a reflected signal, and current to the DUT is starved by the resonator, protecting the DUT from destructive power levels. Measuring the amplitude of the reflected signal at the harmonic frequencies of the RF test signal allows detection of a harmonic knee point for selected reflected signal harmonics, and consequently allows determination of the power level of the RF test signal at which excessive non-linear distortion occurs.Type: ApplicationFiled: December 5, 2018Publication date: June 11, 2020Inventors: Eric S. Shapiro, Tero Tapio Ranta, William Joseph Jasper
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Publication number: 20200051973Abstract: Overcoming parasitic capacitances in RF integrated circuits is a challenging problem. The disclosed methods and devices provide solution to such challenge. Devices based on tunable capacitive elements that can be implemented with switch RF stacks are also disclosed.Type: ApplicationFiled: August 9, 2018Publication date: February 13, 2020Inventors: Eric S. Shapiro, Simon Edward Willard, Tero Tapio Ranta
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Publication number: 20200044642Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.Type: ApplicationFiled: August 12, 2019Publication date: February 6, 2020Inventors: Payman Shanjani, Eric S. Shapiro
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Patent number: 10523195Abstract: Embodiments include a switch stack comprising ACS FETs and mixed-style gate resistor bias networks that mitigate the effects of high leakage current. By carefully selecting the number of ACS FETs in a sub-stack that uses a rung gate resistor bias network versus a sub-stack that uses a rail gate resistor bias network, as well as by selecting particularly useful values for the gate resistors in each bias network, a tradeoff can be achieved between adverse Vg offset and Q factor. The switch stack may be configured with rung-rail gate resistor bias networks, or with rung-rail-rung gate resistor bias networks. Other embodiments include mixed-style body resistor bias networks in switch stacks comprising non-ACS FETs. Some embodiments include one or more positive-logic FETs M1-Mn, series-coupled on at least one end to an “end-cap” FET M0 of a type that turns OFF when the applied VGS is essentially zero volts.Type: GrantFiled: August 2, 2018Date of Patent: December 31, 2019Assignee: pSemi CorporationInventors: Yuan Luo, Matt Allison, Eric S. Shapiro
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Patent number: 10432193Abstract: A switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common port and one or more user ports, any of which may be selectively coupled to the common port by closing an associated path switch; non-selected, unused ports are isolated from the common port by opening an associated path switch. Between each path switch and a port are associated split shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated split absorptive switch module. Each split absorptive switch module includes a split resistor coupled in parallel with a switch. The combination of the split resistor and the switch of the split absorptive switch module is placed in series with a corresponding signal path from each port to the common port.Type: GrantFiled: December 13, 2016Date of Patent: October 1, 2019Assignee: pSemi CorporationInventor: Eric S. Shapiro
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Patent number: 10396772Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.Type: GrantFiled: December 12, 2016Date of Patent: August 27, 2019Assignee: pSemi CorporationInventors: Payman Shanjani, Eric S. Shapiro
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Publication number: 20190199348Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.Type: ApplicationFiled: January 3, 2019Publication date: June 27, 2019Inventors: Eric S. Shapiro, Payman Shanjani