Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: A phase shifter unit cell or a connected set of such cells that can be well isolated from external circuitry and which do not introduce insertion loss into an RF signal path, exhibit good return loss, and further provides additional advantages when combined with bracketing attenuator circuits. More particularly, embodiments integrate a high-isolation function within a phase shifter circuit by breaking the complimentary nature of the control signals to a phase shifter cell to provide greater control of switch states internal to the phase shifter cell and thus enable a distinct high-isolation state, and by including a switchable shunt termination resistor for use in the high-isolation state. Some embodiments are serially coupled to attenuator circuits to enable synergistic interaction that reduces overall die size and/or increases isolation. One such embodiment positions a high-isolation phase shifter cell in accordance with the present invention between bracketing programmable attenuators.

Abstract: An architecture that increases the power that handling capability of the switches within a transceiver is disclosed. An impedance transformation network is introduced at each of the terminals of a transmit/receive switch. Each impedance transformation network transforms the impedance external to the transmit/receive switch to a lower impedance internal to the switch to increase the power handling capability of the transmit/receive switch.

Abstract: An architecture that increases the power that handling capability of the switches within a transceiver is disclosed. An impedance transformation network is introduced at each of the terminals of a transmit/receive switch. Each impedance transformation network transforms the impedance external to the transmit/receive switch to a lower impedance internal to the switch to increase the power handling capability of the transmit/receive switch.

Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Abstract: A phase shifter unit cell or a connected set of such cells that can be well isolated from external circuitry and which do not introduce insertion loss into an RF signal path, exhibit good return loss, and further provides additional advantages when combined with bracketing attenuator circuits. More particularly, embodiments integrate a high-isolation function within a phase shifter circuit by breaking the complimentary nature of the control signals to a phase shifter cell to provide greater control of switch states internal to the phase shifter cell and thus enable a distinct high-isolation state, and by including a switchable shunt termination resistor for use in the high-isolation state. Some embodiments are serially coupled to attenuator circuits to enable synergistic interaction that reduces overall die size and/or increases isolation. One such embodiment positions a high-isolation phase shifter cell in accordance with the present invention between bracketing programmable attenuators.

Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.

Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Abstract: An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits.

Abstract: An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits.

Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Abstract: A switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common port and one or more user ports, any of which may be selectively coupled to the common port by closing an associated path switch; non-selected, unused ports are isolated from the common port by opening an associated path switch. Between each path switch and a port are associated split shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated split absorptive switch module. Each split absorptive switch module includes a split resistor coupled in parallel with a switch. The combination of the split resistor and the switch of the split absorptive switch module is placed in series with a corresponding signal path from each port to the common port.

Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits.

Abstract: A stack of series coupled transistors comprising, at least two sub-portions of the stack of series coupled transistors, and at least one logic decoder coupled to the at least two sub-portions to turn ON at least one sub-portion.

Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.