Abstract: An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.

Abstract: An amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. An ADC is configured to convert the analog error signal into a digital signal in a phase domain. A digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. An output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.

Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: An integrated circuit includes a first and a second conductive path over a substrate, a coil structure over the substrate, a voltage sensing circuit electrically coupled with the coil structure, and a ferromagnetic structure including an open portion. The first conductive path is configured to carry a first time-varying current and to generate a first time-varying magnetic field. The second conductive path is configured to carry a second time-varying current and to generate a second time-varying magnetic field. The first conductive path and the second conductive path extend through the open portion of the ferromagnetic structure. The first conductive path includes a first conductive line below the ferromagnetic structure, a second conductive line above the ferromagnetic structure, and a first via plug coplanar with the ferromagnetic structure, the first via plug electrically coupling the first conductive line and the second conductive line.

Abstract: A class-D amplifier includes an analog-to-digital converter (ADC) configured to generate a first digital signal based on an analog input signal and a feedback signal received at an input node. A loop filter is configured to modify the first digital signal by moving an error of the ADC out of a predetermined frequency band, and a compensation filter is configured to further modify the first digital signal by introducing one or more poles or zeros, thereby generating a second digital signal. An output circuit is configured to generate an output signal at an output node based on the second digital signal, and the feedback signal is generated from the output signal.

Abstract: An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

Abstract: A DC-DC converter and a DC-DC converter operation method are provided. The DC-DC converter includes a power stage, an error amplifier, a pulse width modulation (PWM) generator, and a gate controller. The power stage includes a first transistor and a second transistor. The power stage is configured to generate an output at a first node. The error amplifier is configured to receive the output from the first node and generates an error signal. The PWM generator is configured to receive the error signal from the error amplifier and generates a pulse width modulation signal. The gate controller includes a plurality of voltage dividers and a comparator. The voltage dividers are configured to perform a voltage division on the first node and a second node to generate a first voltage and a second voltage. The first node is an output node of the DC-DC converter and the second node is a node between the first transistor and the second transistor of the DC-DC converter.

Abstract: An integrated circuit includes a substrate, a first conductive path over the substrate, a coil structure over the substrate, and a voltage sensing circuit electrically coupled with the coil structure. The first conductive path is configured to carry a first time-varying current and to generate a first time-varying magnetic field based on the first time-varying current. The coil structure is magnetically coupled with the first conductive path through the first time-varying magnetic field and is configured to generate an induced electrical potential responsive to the first time-varying magnetic field. The voltage sensing circuit is configured to measure a voltage level of the induced electrical potential.

Abstract: An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to output a first digital value corresponding to an analog input voltage. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first current signal and the second current signal in the current domain, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values into a digital output voltage.

Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

Abstract: A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.

Abstract: A class-D amplifier includes an analog-to-digital converter (ADC) configured to generate a first digital signal based on an analog input signal and a feedback signal received at an input node. A loop filter is configured to modify the first digital signal by moving an error of the ADC out of a predetermined frequency band, and a compensation filter is configured to further modify the first digital signal by introducing one or more poles or zeros, thereby generating a second digital signal. An output circuit is configured to generate an output signal at an output node based on the second digital signal, and the feedback signal is generated from the output signal.

Abstract: An integrated transformer is disclosed. The integrated transformer includes a magnetic core situated in a first layer from among multiple layers of a semiconductor layer stack, a first conductor and a second conductor from among multiple conductors, and a via. The first conductor is situated within a second layer, above the first layer, from among the multiple layers of the semiconductor layer stack. The second conductor is situated within a third layer, below the first layer, from among the multiple layers of the semiconductor layer stack. The via physically and electrically connects the first conductor and the second conductor. The via, the first conductor, and the second conductor form a primary winding of the integrated transformer. The integrated transformer additionally includes a secondary winding, wrapped around the magnetic core, situated in the first layer, the second layer, and the third layer.

Abstract: An integrated circuit (IC) package structure includes an electrical signal path, a low thermal resistance path and a substrate that includes a first device and a second device. The first device and the second device are part of an IC chip. The electrical signal path is from the first device to a top surface of the IC chip. The low thermal resistance path extends from the second device to the top surface of the IC chip. The low thermal resistance path is electrically isolated from the electrical signal path. The second device is thermally coupled to the first device by a low thermal resistance substrate path.