Abstract: A regulator circuit comprises: a regulator output node; at least (N+1) regulator control circuits, N being an integer greater than 1; N drivers, each one of the N drivers including: a multiplexer having an input port and an output port, the input port of the multiplexer being coupled with output nodes of the at least (N+1) regulator control circuits; an adjuster circuit configured to adjust a level of a current supplied by the driver to the regulator output node; and a task controller. The task controller is configured to: set a first one of the N+1 regulator control circuits to be idle during a first cycle of a clock signal; and set a second one of the N+1 regulator control circuits to be idle during a second cycle of the clock signal.

Abstract: A power converter includes a first load terminal used to supply a current to a load and a second load terminal used to return a feedback voltage based on the current. A calibration circuit supplies a calibrated voltage processed from the feedback voltage, and a hysteretic comparator controls a current level of the current based on a difference between the feedback voltage and the calibrated voltage.

Abstract: A multi-phase buck converter comprises a first comparator, a second comparator and a counter. The first comparator has a first node connected to a first voltage reference and a second node. The second comparator has a first node connected to a second voltage reference and a second node. The second node of the second comparator and the second node of the first comparator are together connected to an input voltage from an active phase of the buck converter. The counter is configured to adjust a number of active phases of the buck converter based on the input voltage.

Abstract: Various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (MTF) materials. During operation, an electric field passes through one or mare conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. The magnetic thin film (MTF) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. As a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more MTF materials.

Abstract: An analog-to-digital converter (ADC) circuit includes a first ADC stage comprising a first successive approximation register (SAR) circuit that is configured to convert a current analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a current digital output signal, and to generate a residual voltage corresponding to a voltage value difference between the current analog input signal and the first digital signal; a second ADC stage, coupled to the first ADC stage, comprising an amplifier circuit that is configured to amplify the residual voltage; and a third ADC stage, coupled to the second ADC stage, comprising a second SAR circuit that is configured to convert the amplified residual voltage into a second digital signal corresponding to a least-significant-bits (LSB) portion of the current digital output signal when the first SAR circuit receives a subsequent analog input signal.

Abstract: An analog-to-digital converter (ADC) circuit includes a first ADC stage comprising a first successive approximation register (SAR) circuit that is configured to convert a current analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a current digital output signal, and to generate a residual voltage corresponding to a voltage value difference between the current analog input signal and the first digital signal; a second ADC stage, coupled to the first ADC stage, comprising an amplifier circuit that is configured to amplify the residual voltage; and a third ADC stage, coupled to the second ADC stage, comprising a second SAR circuit that is configured to convert the amplified residual voltage into a second digital signal corresponding to a least-significant-bits (LSB) portion of the current digital output signal when the first SAR circuit receives a subsequent analog input signal.

Abstract: A high accuracy on-chip thermal sensor includes an integrated circuit and sensing elements. The thermal sensor finds application in various mobile and battery powered devices and includes a processor that analyzes a measured temperature signal and decides if the thermal sensor operates in low or high power operational mode, or if the device's CPU is to be reset. A method utilizing the thermal sensor includes making comparisons to two threshold temperatures and operating at low power mode below the first threshold temperature, high power mode between the two threshold temperatures and causing reset if the second threshold temperature is exceeded. Low power operational mode includes a lower clock frequency, lower bias current and lower power consumption. Higher power operational mode is used when the upper threshold temperature is being approached and includes a higher data sampling frequency and more accurate temperature control and uses higher power.

Abstract: A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.

Abstract: The present disclosure relates to voltage regulation techniques. In some embodiments, a voltage regulator is configured to regulate an output voltage based on a reference voltage. The voltage regulator comprises an analog-to-digital converter, an encoder, a decoder and a power stage. The analog-to-digital converter receives the reference voltage and an output voltage of the voltage regulator and provides a digital error signal. The encoder is coupled to the analog-to-digital converter output and configured to provide a multi-bit digital control signal based upon a present value of the digital error signal, a plurality of pre-determined coefficients, and a plurality of previous values of the digital error signal. The decoder is coupled to the encoder and configured to generate a plurality of control signals based on the multi-bit digital control signal. The power stage comprises a plurality of power cells which are coupled to a power supply and which receive the plurality of control signals, respectively.

Abstract: A multi-phase buck converter comprises a first comparator, a second comparator and a counter. The first comparator has a first node connected to a first voltage reference and a second node. The second comparator has a first node connected to a second voltage reference and a second node. The second node of the second comparator and the second node of the first comparator are together connected to an input voltage from an active phase of the buck converter. The counter is configured to adjust a number of active phases of the buck converter based on the input voltage.

Abstract: A circuit includes a first integration stage, a quantizer, a second integration stage coupled between the first integration stage and the quantizer, and a digital-to-analog converter (DAC). The first integration stage includes a first input node pair configured to receive a pair of differential analog input signals, and the quantizer is configured to generate a digital signal based on the pair of differential analog input signals and a clock signal. The second integration stage includes a second input node pair, and the DAC is configured to receive the digital signal and output feedback signals to at least one input node pair of the first input node pair or the second input node pair.

Abstract: A circuit includes a first circuit that operates at a first-circuit supply voltage value and generates at least one of a first reference voltage value or a second reference voltage value, based on a voltage rated for transistors in a second circuit. The second circuit operates at the first-circuit supply voltage value and receives a first signal and at least one of the first reference voltage value or the second reference voltage value. The first signal is configured to swing between a low voltage value and a high voltage value lower than the first-circuit supply voltage value. The second circuit keeps a voltage across two terminals of a first transistor in the second circuit below the voltage rated for the first transistor, based on the at least one of the first reference voltage value or the second voltage value.

Abstract: A Class-D amplifier includes an analog-to-digital converter (ADC) having a first input node. The ADC receives a first analog input signal and a first feedback signal at the first input node and generates a first digital signal based on the first analog input signal and the first feedback signal. A digital filter generates a second digital signal based on the first digital signal. An output circuit includes a first output node, the output circuit being configured to generate a first output signal at the first output node based on the second digital signal. A first feedback unit generates the first feedback signal as the first output signal scaled by a gain factor having a constant value in the Z-domain.

Abstract: A regulator includes a controller, a driving unit, a digital-to-analog converter, and a comparator. The controller outputs a digital reference voltage and a control signal responsive to a comparison signal. The driving unit generates an output voltage at a first node responsive to the control signal. The digital-to-analog converter generates an analog reference voltage responsive to the digital reference voltage. The comparator generates the comparison signal based on the analog reference voltage and the output voltage.

Abstract: A circuit comprises a first circuit and a second circuit. The first circuit is configured to operate at a first-circuit supply voltage value, and to generate a first reference voltage value based on a voltage rated for transistors in a second circuit. The second circuit is configured to operate at a second-circuit supply voltage value, to receive a first signal and the first reference voltage value, and to clamp an input node of the second circuit based on the first reference voltage value. The second-circuit supply voltage value is less than the first-circuit supply voltage value. The first signal is configured to swing between a low voltage value and a voltage value higher than the second-circuit supply voltage value.

Abstract: An integrated transformer is disclosed. The integrated transformer includes a magnetic core situated in a first layer from among multiple layers of a semiconductor layer stack, a first conductor and a second conductor from among multiple conductors, and a via. The first conductor is situated within a second layer, above the first layer, from among the multiple layers of the semiconductor layer stack. The second conductor is situated within a third layer, below the first layer, from among the multiple layers of the semiconductor layer stack. The via physically and electrically connects the first conductor and the second conductor. The via, the first conductor, and the second conductor form a primary winding of the integrated transformer. The integrated transformer additionally includes a secondary winding, wrapped around the magnetic core, situated in the first layer, the second layer, and the third layer.

Abstract: A regulator circuit comprises: a regulator output node; at least (N+1) regulator control circuits, N being an integer greater than 1; N drivers, each one of the N drivers including: a multiplexer having an input port and an output port, the input port of the multiplexer being coupled with output nodes of the at least (N+1) regulator control circuits; an adjuster circuit configured to adjust a level of a current supplied by the driver to the regulator output node; and a task controller. The task controller is configured to: set a first one of the N+1 regulator control circuits to be idle during a first cycle of a clock signal; and set a second one of the N+1 regulator control circuits to be idle during a second cycle of the clock signal.

Abstract: A comparator circuit includes a comparator, a first selection circuit, and a switched-capacitor circuit. The comparator has a first terminal, a second terminal, and an output terminal. The comparator is configured to generate an output signal at the output terminal based on a first signal on the first terminal and a second signal on the second terminal. The first selection circuit is coupled with the first terminal of the comparator and configured to selectively set a first input signal or a first calibration signal as the first signal in response to a control signal. The switched-capacitor circuit is coupled with the output terminal and the second terminal of the comparator. The switched-capacitor circuit is configured to adjust and output the second signal based on the output signal.

Abstract: A voltage regulator circuit includes a comparator configured to compare whether an output voltage of the voltage regulator circuit is either equal to or less than a reference voltage; a control unit, coupled to the comparator, and configured to use a duty ratio of the output voltage to an input voltage of the control unit to estimate a time period; a first transistor, coupled to the control unit, and configured to be selectively turned on based on the estimated time period; and an inductor, coupled to the first transistor, configured to conduct an inductor current, wherein when the comparator determines that the output voltage is either equal to or less than the reference voltage, the first transistor is turned on during the estimated time period to allow the inductor current to be increased so as to accordingly increase the output voltage.

Abstract: A converter includes a plurality of active circuitry elements over a substrate. The converter further includes a passivation structure over the plurality of active circuitry elements, the passivation structure having at least one opening that is configured to expose at least one electrical pad of each active circuitry element. The converter further includes a plurality of passive electrical components over the passivation structure, wherein each passive electrical component is selectively connectable with at least one other passive electrical component, and a first side of each passive electrical component is electrically coupled to an electrical pad of each of at least two active circuitry elements.