Patents by Inventor Erich F Haratsch

Erich F Haratsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BAD MEMORY UNIT DETECTION IN A SOLID STATE DRIVE
    Publication number: 20150287478
    Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to determine which of the memory units to mark as bad based on a test of whether a unit of memory larger than a block of the memory has failed. The test is based on a threshold of the bad blocks in the unit of memory.
    Type: Application
    Filed: April 28, 2014
    Publication date: October 8, 2015
    Applicant: LSI Corporation
    Inventors: Zhengang Chen, Earl T. Cohen, Erich F. Haratsch, Jeremy Werner
  • ERROR CORRECTION CODE (ECC) SELECTION IN NAND FLASH CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES
    Publication number: 20150286528
    Abstract: An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined data characterizing distribution properties of each of the plurality of error correction codes.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 8, 2015
    Applicant: LSI Corporation
    Inventors: Yu Cai, Yunxiang Wu, Erich F. Haratsch
  • READ POLICY FOR SYSTEM DATA OF SOLID STATE DRIVES
    Publication number: 20150286421
    Abstract: An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies.
    Type: Application
    Filed: May 5, 2014
    Publication date: October 8, 2015
    Applicant: LSI Corporation
    Inventors: Zhengang Chen, Gordon J. Coleman, Earl T. Cohen, Ivana Djurdjevic, Erich F. Haratsch
  • Systems and Methods for Differential Message Scaling in a Decoding Process
    Publication number: 20150286523
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 8, 2015
    Applicant: LSI Corporation
    Inventors: Yu Cai, Yunxiang Wu, Erich F. Haratsch, Ning Chen
  • FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE
    Publication number: 20150278015
    Abstract: An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.
    Type: Application
    Filed: April 28, 2015
    Publication date: October 1, 2015
    Inventors: Erich F. Haratsch, Jeremy Werner, Zhengang Chen, Earl T. Cohen, Yunxiang Wu, Ning Chen
  • MANUFACTURER SELF-TEST FOR SOLID-STATE DRIVES
    Publication number: 20150262712
    Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to blocks of the memory that are not marked as bad on a block list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to perform a plurality of scans on the memory. The scans are configured to (a) identify the bad blocks, and (b) mark the bad blocks as bad on the block list.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 17, 2015
    Inventors: Zhengang Chen, David Patmore, Yingji JU, Erich F. Haratsch
  • Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding
    Patent number: 9135999
    Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: September 15, 2015
    Assignee: Seagate Technology LLC
    Inventors: Harley F. Burger, Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Policy for read operations addressing on-the-fly decoding failure in non-volatile memory
    Patent number: 9135112
    Abstract: An apparatus includes a non-volatile memory and a controller. The controller is operatively coupled to the non-volatile memory and configured to perform read and write operations on the non-volatile memory using codewords as a unit of read access. The controller includes an error correction engine configured to perform an error correction on codewords read from the non-volatile memory, and, if the error correction fails, to perform one or more retry procedures. The controller is further configured to perform one or more background procedures as a result of the error correction or one or more of the retry procedures not being successful and send an error message as a result of all of the retry procedures not being successful. The one or more background procedures are directed to determining a cause of the error correction failure.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 15, 2015
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Earl T. Cohen, Jeremy Werner, Erich F. Haratsch
  • SOFT DECODING OF POLAR CODES
    Publication number: 20150256196
    Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 10, 2015
    Applicant: LSI Corporation
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Yue Li
  • ADJUSTING LOG LIKELIHOOD RATIO VALUES TO COMPENSATE MISPLACEMENT OF READ VOLTAGES
    Publication number: 20150243363
    Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values.
    Type: Application
    Filed: March 3, 2014
    Publication date: August 27, 2015
    Applicant: LSI Corporation
    Inventors: Yunxiang Wu, Zhengang Chen, AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • REDUCED POLAR CODES
    Publication number: 20150236715
    Abstract: A method for encoding a reduced polar code is disclosed. The method generally includes (a) modifying an input codeword including polar code encoded input data by removing one or more bits from one of (i) a first part of the input codeword and (ii) a second part of the input codeword and (b) generating an output codeword by concatenating the first and the second parts of the modified input codeword.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 20, 2015
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Yue Li
  • Refresh, Run, Aggregate Decoder Recovery
    Publication number: 20150236726
    Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
    Type: Application
    Filed: March 18, 2014
    Publication date: August 20, 2015
    Applicant: LSI Corporation
    Inventors: Sundararajan Sankaranarayanan, AbdelHakim S. Alhussien, Erich F. Haratsch, Earl Cohen
  • SYSTEM TO CONTROL A WIDTH OF A PROGRAMMING THRESHOLD VOLTAGE DISTRIBUTION WIDTH WHEN WRITING HOT-READ DATA
    Publication number: 20150235705
    Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to write user data using a plurality of threshold voltages. The data considered hot-read data is written using a first voltage threshold. The data not considered hot-read data is written using a second voltage threshold. The first voltage threshold reduces an impact on endurance of the memory.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 20, 2015
    Applicant: LSI Corporation
    Inventors: Yu Cai, Yunxiang Wu, Erich F. Haratsch
  • Systems and Methods for Last Written Page Handling in a Memory Device
    Publication number: 20150227314
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 13, 2015
    Applicant: LSI Corporation
    Inventors: Zhengang Chen, Yu Cai, Erich F. Haratsch, Zhimin Dong
  • HOT-READ DATA AGGREGATION AND CODE SELECTION
    Publication number: 20150227418
    Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 13, 2015
    Applicant: LSI Corporation
    Inventors: Yu Cai, Yunxiang Wu, Erich F. Haratsch
  • MITIGATION OF WRITE ERRORS IN MULTI-LEVEL CELL FLASH MEMORY THROUGH ADAPTIVE ERROR CORRECTION CODE DECODING
    Publication number: 20150229337
    Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.
    Type: Application
    Filed: February 28, 2014
    Publication date: August 13, 2015
    Applicant: LSI Corporation
    Inventors: AbdelHakim S. Alhussien, Ivana Djurdjevic, Yu Cai, Erich F. Haratsch, Yue Li, Earl T. Cohen
  • Encoding and decoding in flash memories using convolutional-type low-density parity check codes
    Patent number: 9106264
    Abstract: Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: August 11, 2015
    Inventors: Abdel Hakim S. Alhussien, Erich F. Haratsch, Zongwang Li, Fan Zhang
  • Systems and Methods for Hard Error Reduction in a Solid State Memory Device
    Publication number: 20150220388
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.
    Type: Application
    Filed: February 11, 2014
    Publication date: August 6, 2015
    Applicant: LSI Corporation
    Inventors: Yunxiang Wu, Yu Cai, Erich F. Haratsch
  • Detection and decoding in flash memories with selective binary and non-binary decoding
    Patent number: 9086984
    Abstract: Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting; the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and jointly decoding the plurality of bits using the non-binary log likelihood ratio, wherein the pages are encoded independently.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 21, 2015
    Assignee: Seagate Technology LLC
    Inventors: Abdel Hakim S. Alhussien, Zongwang Li, Erich F. Haratsch, Ludovic Danjean
  • FRAMEWORK FOR BALANCING ROBUSTNESS AND LATENCY DURING COLLECTION OF STATISTICS FROM SOFT READS
    Publication number: 20150199149
    Abstract: An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block.
    Type: Application
    Filed: February 17, 2014
    Publication date: July 16, 2015
    Applicant: LSI Corporation
    Inventors: Sundararajan Sankaranarayanan, Erich F. Haratsch