Abstract: An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

Abstract: An apparatus having a memory and a controller is disclosed. The memory is configured to (i) program a protected lower unit in a lower page of a location, (ii) generate a corrected lower unit by correcting the protected lower unit using a first error correction code and (iii) program a protected upper unit in an upper page of the location based on the corrected lower unit. The controller is configured to generate the protected upper unit by encoding an upper write data item using a second error correction code. The controller is on a separate die as the memory.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to write user data using a plurality of threshold voltages. The data considered hot-read data is written using a first voltage threshold. The data not considered hot-read data is written using a second voltage threshold. The first voltage threshold reduces an impact on endurance of the memory.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to recover data stored in the memory determined to exceed a maximum number of errors after performing a first read operation using a first read reference voltage. The controller may perform a second read operation using a second read reference voltage. The controller may identify a victim cell having a threshold voltage in a region between the first read reference voltage and the second read reference voltage. The controller may perform a third read operation on aggressor cells of the victim cell. The controller may perform a fourth read operation using the first read reference voltage with bit-fixed values on the victim cell based on a type of interference from the aggressor cells.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a plurality of reads on a victim cell. The controller may be configured to store measured victim information from the plurality of reads on the victim cell. The controller may be configured to perform one or more reads on a plurality of aggressor cells. The controller may be configured to store measured aggressor information from the one or more reads on the plurality of aggressor cells. The controller may be configured to generate inter-cell interference parameters based on the measured victim information and the measured aggressor information. The controller may be configured to mitigate inter-cell interference based on the inter-cell interference parameters.

Abstract: An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.

Abstract: An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

Abstract: An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.

Abstract: A method for encoding a reduced polar code is disclosed. The method generally includes (a) modifying an input codeword including polar code encoded input data by removing one or more bits from one of (i) a first part of the input codeword and (ii) a second part of the input codeword and (b) generating an output codeword by concatenating the first and the second parts of the modified input codeword.

Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

Abstract: Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units. The memory units may each have a size less than a total size of the memory. The memory units may include a plurality of cells. The controller may be configured to issue a plurality of program operations to write to one or more of the cells. The controller may be configured to implement a polling status command after each of the program operations to verify programming of each of the cells. A response to each of the polling status commands may be used to report a number of the cells that failed to be programmed.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error correction code decoding fails. The controller may be configured to generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold. The plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units.

Abstract: A flash memory controller having soft-decoding error correcting code (ECC) logic generates log likelihood ratio or similar ECC decoder soft input information from decision patterns obtained from reading data from the same portion of flash memory two or more times. Each decision pattern corresponds to a voltage region bordering one of the reference voltages. Each decision pattern represents a combination of flash memory bit value decisions for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell. Numerical values are then computed in response to combinations of the flash memory bit value decisions represented by the decision patterns. The numerical values are provided to the soft-decoding ECC logic to serve as soft input information.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for perturbing soft data in a layered decoder system.

Abstract: An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page.

Abstract: Aspects of the disclosure pertain to methods and systems that are configured to handle excessive read noise in soft read systems. In an implementation, a method includes determining a number of unexpected patterns of a soft read of a memory cell after a soft decoding failure. The method also includes determining whether the number of unexpected patterns is greater than a threshold number of unexpected patterns. When it is determined that the number of unexpected patterns is greater than the threshold number of unexpected patterns, the method at least one of: performing at least one more soft read of the memory cell with a larger read voltage spacing than an initial read that produced the soft decoding failure; and discarding a result of one or more soft reads of the memory cell and utilizing a remainder of results of respective other soft reads of the memory.

Abstract: A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells.