Patents by Inventor Eu-Joon BYUN

Eu-Joon BYUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11639969
    Abstract: A data processing system includes: a host suitable for checking battery state information and determining a battery grade based on the battery state information; and a memory system suitable for storing information indicating the battery grade provided from the host, determining a method of performing a background operation based on the battery grade, and performing the background operation based on the determined method.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: May 2, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Publication number: 20230116156
    Abstract: Embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may generate a fused linked list which includes information of a plurality of write commands received from a host and a plurality of synchronization commands requesting a synchronization operation, and control the synchronization operation for one or more of the plurality of write commands based on the fused linked list.
    Type: Application
    Filed: April 25, 2022
    Publication date: April 13, 2023
    Inventor: Eu Joon BYUN
  • Patent number: 11625178
    Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having improved zone recovery speed may include a memory device including a plurality of memory blocks, and a memory controller configured to, in response to the zone open request, allocate memory blocks to store data of a logical address group corresponding to an open-requested zone among the plurality of memory blocks, and control the memory device to store zone recovery information included in a zone open request, and wherein the zone recovery information indicates whether data to be stored in the open-requested zone is to be recovered in a next power cycle.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: April 11, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11609710
    Abstract: A data processing system may include: a host including a command queue including a plurality of command storage areas, and configured to store summary information of a second command among a plurality of commands in a reserved storage area of a command storage area, among the plurality of command storage areas, in which a first command among the plurality of commands being a previous command to the second command is stored, when inserting the second command into the command queue; and a data storage device configured to fetch the first command from the command queue and store the fetched first command, according to a new command notification received from the host.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: March 21, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11561712
    Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved physical address obtainment speed may include a nonvolatile memory device configured to store map data including a plurality of map segments including mapping information and, a volatile memory device including a first map cache area temporarily storing the map data configured by map entries each corresponding to one logical address, and a second map cache area temporarily storing the map data configured by map indexes each corresponding to a plurality of logical addresses.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: January 24, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11561725
    Abstract: Embodiments of the present disclosure relate to a system and an operating method thereof. According to embodiments of the present disclosure, a memory system may transmit a first type response indicating that first data has been cached in a cache to the host when receiving a first command requesting to write the first data from the host, and may transmit a second type response indicating success or failure of an operation of storing the first data in the memory device to the host after transmitting the first type response to the host. Further, the host may delete the first data from a write buffer after the operation of storing the first data in the memory device succeeds.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 24, 2023
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun
  • Patent number: 11550578
    Abstract: A data storage apparatus includes a storage device; a controller to control data input and output operations of the storage device; and a swap memory provided in an outside of the controller, wherein the controller includes a thread manager to perform a preparation operation on a first thread included in a task in response to a request for processing the task, request the storage device to process the first thread on which the preparation operation has been performed, perform a preparation operation on at least one subsequent thread following the first thread while the storage device processes the first thread, and store context data of the first thread and the at least one subsequent thread in the swap memory, wherein the task includes the first thread and the at least one subsequent thread, and the preparation operation includes an address mapping operation.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc
    Inventors: Hye Mi Kang, Eu Joon Byun
  • Patent number: 11550662
    Abstract: The present technology relates to an electronic device. More specifically, the present technology relates to a storage device and a computing system. A storage device according to an embodiment may include a memory device including a firmware block group configured to store main firmware data and sub firmware data, and a user block group configured to store write data, and a memory controller, in response to a booting request provided from a host, configured to count a number of previously generated power losses based on data stored in an open block in the user block group in a booted state based on the main firmware data, performs a rebooting operation using the sub firmware data when the number of power losses exceeds a reference number, and execute sub firmware to correct an error of data related to the power losses.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Publication number: 20230004325
    Abstract: A data processing system in which, in a case where it is difficult for a host to perform garbage collection by itself due to a load induced in the host in a system configured by Zoned Namespaces, the host requests garbage collection to a memory system and thus the memory system performs the garbage collection, and an operating method thereof.
    Type: Application
    Filed: February 16, 2022
    Publication date: January 5, 2023
    Inventor: Eu Joon BYUN
  • Patent number: 11537483
    Abstract: A method for operating a controller that controls a memory device includes: replacing a bad block of a superblock with a replacement block to form a reproduced superblock; controlling the memory device to perform a program operation on the reproduced superblock according to an interleaving scheme; moving data stored in the replacement block to a pseudo-replacement block when the program operation on the reproduced superblock is completed; and releasing the replacement block from the reproduced superblock.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: December 27, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Publication number: 20220398040
    Abstract: The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.
    Type: Application
    Filed: November 22, 2021
    Publication date: December 15, 2022
    Inventors: Hye Mi KANG, Eu Joon BYUN
  • Patent number: 11526438
    Abstract: An operation method of a controller, comprising: selecting a target super block, on which garbage collection (GC) is to be performed, among a plurality of super blocks which are completely programmed, based on a first valid page count of each of the super blocks when a determination to perform GC is made; selecting a first target block among a plurality of memory blocks in the target super block based on a second valid-page decrease amount of each of the memory blocks; and performing a first copy operation on valid pages in the first target block.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: December 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Publication number: 20220391093
    Abstract: Disclosed are a data processing system comprising: a memory system for providing a host with a memory map segment including map pieces; and the host for storing the memory map segment as a host map segment and converting a logical address into a physical address using the host map segment. The memory system stores changed map pieces in a map cache, inserts the changed map pieces in a response to a first command, and provides the host with the response. The host updates the host map segment based on the changed map pieces. When a read command includes a logical address and a physical address, the memory system accesses a memory device using the physical address of the read command according to whether the logical address of the read command is stored in the map cache.
    Type: Application
    Filed: October 20, 2021
    Publication date: December 8, 2022
    Inventors: Hye Mi KANG, Eu Joon BYUN
  • Patent number: 11520519
    Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller may include a command processor configured to generate a flush command in response to a flush request and determine flush data chunks to be stored, a write operation controller configured to control memory devices to perform a first program operation of storing flush data chunks, and to perform a second program operation of storing data corresponding to a write request that is input later than the flush request, regardless of whether a response to the flush command has been provided to a host, and a flush response controller configured to, when the first program operation is completed, provide a response to the flush command to the host depending on whether responses to flush commands, input earlier than the flush command, have been provided to the host.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 6, 2022
    Assignee: SK hynix Inc.
    Inventors: Byung Jun Kim, Eu Joon Byun, Hye Mi Kang
  • Patent number: 11513946
    Abstract: A memory controller includes a mapping data control unit configured to interrupt the generation of the additional mapping data, when during generation of additional mapping data, an operation for an address identical to a logical block address in the additional mapping data is performed, and to generate dummy mapping data. The additional mapping data may include mapping information indicating a mapping relationship between a logical block address and a physical block address.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Publication number: 20220365884
    Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a host configured to generate and output a host command and a host address and to receive and store host map data, a controller configured to store map data, generate an internal command in response to the host command, and map the host address to an internal address based on the map data, and a memory device configured to perform an operation in response to the internal command and the internal address, wherein the controller is configured to load, when the map data corresponding to the host address is not stored in the controller, new map data into a map data storage area storing map data that is identical to the host map data.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventor: Eu Joon BYUN
  • Patent number: 11500771
    Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system performs an operation of recovering system data lost due to SPO when an SPO recovery operation is performed, and flushes recovered system data into the memory device after a first time point at which the operation of recovering the system data is completed and before a second time point at which a power off preparation request is received from a host.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11487658
    Abstract: A memory system may include a plurality of dies; and a controller coupled to the plurality of dies through a plurality of data paths, the controller being suitable for transmitting first data received from a host and second data obtained through an internal operation in parallel through the plurality of data paths.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Publication number: 20220334962
    Abstract: A memory system may comprise: a memory device including a plurality of memory dies; and a controller including a first memory, Wherein the controller may store data segments of user data, corresponding to a plurality of commands received from a host, in the first memory, controls the memory device to sequentially store the data segments in the memory dies through interleaving, may update map segments of map data corresponding to storage of the data segments in the memory dies, may store the map segments in the first memory, controls the memory device to store the map segments stored in the first memory in the memory dies, and may assist the host in storing the map segments, stored in the first memory, in a second memory in the host.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventor: Eu-Joon BYUN
  • Publication number: 20220300433
    Abstract: A memory system may include: a nonvolatile memory device; and a controller suitable for generating first map information which maps physical addresses of the nonvolatile memory device to logical addresses received from a host, selecting some segments of the first map information as second map information, and outputting the second map information to the host, the controller may determine whether the second map information is updated, and may determine updated map segments as third map information, and the controller may output information to the host indicating the third map information corresponding to a command received from the host.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventor: Eu-Joon BYUN