Patents by Inventor Eu-Joon BYUN

Eu-Joon BYUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory controller having improved map data access performance and method of operating the same
    Patent number: 11194736
    Abstract: A memory controller may include a map cache configured to store one or more of a plurality of map data sub-segments respectively corresponding to a plurality of sub-areas included in each of the plurality of areas, and a map data manager configured to generate information about a map data sub-segment to be provided to a host and which is determined based on a read count for the memory device, and generate information about a map data segment to be deleted from the host and which is determined based on the read count for the memory device and a memory of the host.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun
  • APPARATUS AND METHOD FOR INCREASING OPERATION EFFICIENCY IN DATA PROCESSING SYSTEM
    Publication number: 20210365183
    Abstract: A data processing system may include: a memory system comprising a memory device including a plurality of memory blocks; and a host suitable for dividing the memory device into a plurality of logical blocks, and including a plurality of segments each constituted by at least some of the plurality of logical blocks. The host may select a victim segment based on the number of the valid logical blocks corresponding to each of the memory blocks, and perform segment recycling on the victim segment, and one or more memory blocks may be invalidated by the segment recycling.
    Type: Application
    Filed: January 25, 2021
    Publication date: November 25, 2021
    Inventor: Eu Joon BYUN
  • Memory system for flexible map block management and operating method thereof
    Patent number: 11169721
    Abstract: A memory system may include a memory device including a plurality of memory blocks; and a controller suitable for controlling the memory device. The controller may include a monitor suitable for monitoring valid data ratios of a first area and a second area and a processor suitable for comparing a first valid data ratio of the first area to a first threshold value, comparing a second valid data ratio of the second area to a second threshold value, and reallocating a target reserved memory block, which is allocated to the second area, to the first area according to the two comparison results.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • DATA PROCESSING SYSTEM INCLUDING PLURALITY OF MEMORY SYSTEMS
    Publication number: 20210342083
    Abstract: A data processing apparatus includes a first memory system including first and second interfaces and a first storage region, coupled to a host through the first interface, and configured to set a size of logical-to-physical (L2P) mapping of the first storage region to a first size unit; and a second memory system including a third interface coupled to the second interface to communicate with the first memory system, and configured to transmit capacity information for a second storage region included therein to the first memory system according to a request of the first memory system during an initial operation period, and set a size of logical-to-physical (L2P) mapping of the second storage region to a second size unit in response to a map setting command transmitted from the first memory system during the initial operation period.
    Type: Application
    Filed: October 30, 2020
    Publication date: November 4, 2021
    Inventor: Eu Joon BYUN
  • Memory system and method of operating the same
    Patent number: 11163491
    Abstract: Provided herein is a memory system and a method of operating the memory system. The memory system may include: a memory device including a plurality of memory blocks; and a controller configured to control the memory device to perform a read operation in response to a host command, and configured to control a read reclaim operation based on a read count of each of the plurality of memory blocks. During the read reclaim operation, the controller may select a program mode of a target memory block depending on the amount of valid data read from a victim memory block, and control the memory device to store the valid data in the target memory block based on the selected program mode.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Controller, memory system and operating method thereof for controlling a non-volatile memory device during a sync-up operation
    Patent number: 11163696
    Abstract: Various embodiments generally relate to a semiconductor device, and more particularly, to a controller, a memory system and an operating method thereof. In an embodiment of the present disclosure, a controller for controlling a nonvolatile memory device may perform a sync-up operation of transmitting a logical-to-physical (L2P) map segment to a host to update the L2P map segment stored in a host memory included in the host when a map data changing event occurs, register the L2P map segment transmitted to the host and time information at which the sync-up operation is performed in a sync-up management list, calculate a sync-up period based on the time information, and perform the sync-up operation on an L2P map segment having a sync-up period greater than a threshold time, among L2P map segments registered in the sync-up management list.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • ELECTRONIC DEVICE, DATA STORAGE DEVICE AND METHOD OF OPERATING THEREFOR
    Publication number: 20210326053
    Abstract: An electronic device may include a plurality of data storage devices including a master storage device and one or more slave storage devices. Each of the data storage devices comprises a storage configured to store data and a controller configured to control data input/output operations with respect to the corresponding storage. The controller of the master storage device receives device information including identification information, capacity information and physical configuration information from each of the slave storage devices, and the controller of the master storage device changes an electric power mode of at least one of the slave storage devices selected based on capacity margin of the master storage device and the device information.
    Type: Application
    Filed: September 16, 2020
    Publication date: October 21, 2021
    Inventor: Eu Joon BYUN
  • Apparatus and method for transmitting map data in memory system
    Patent number: 11144478
    Abstract: An operation method of a memory system includes: searching for a valid physical address in memory map segments stored in the memory system, based on a read request from a host, a logical address corresponding to the read requests, and a physical address corresponding to the logical address and performing a read operation corresponding to the read request; caching some of the memory map segments in the host as host map segments based on a read count threshold indicating the number of receptions of the read request for the logical address; and adjusting the read count threshold based on a miss count indicating the number of receptions of the read request with no physical address, and a provision count indicating the number of times the memory map segment is cached in the host.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Memory system and operation method thereof
    Patent number: 11144449
    Abstract: An operation method of a memory system includes a memory device including plural level memory cells. The operation method includes allocating a physical address according to a physical address allocation scheme which is determined based on an attribute of a write command; and performing a write operation on the allocated physical address.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Memory system using available bad block based on data storage reliability and operating method thereof
    Patent number: 11144246
    Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks and a controller configured to control the nonvolatile memory device. The controller determines, as an available bad block, a memory block having data storage reliability equal to or greater than a first reference value, included in the plurality of memory blocks, determines write data to be stored in the nonvolatile memory device as first data which is required for the memory system to normally operate or second data which does not correspond to the first data, and allocate the write data determined as the second data to the available bad block. The nonvolatile memory device performs a write operation of storing the second data in the available bad block.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Memory system performing check pointing operation and operating method thereof
    Patent number: 11144406
    Abstract: A memory system includes a plurality of dies including a plurality of memory blocks, each die including a first region and a second region; and a controller which includes a memory storing plural pieces of check point information and a processor, wherein the processor includes: a check point manager suitable for performing a check pointing operation by programming identification information and check point information on the plurality of memory blocks, according to the size of the plural pieces of; and a recovery manager suitable for resuming an operation stopped due to a sudden power-off (SPO) by using last check point information and last identification information, which are programmed last in memory blocks in each of the dies when the SPO occurs.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Memory controller and method of operating the same
    Patent number: 11139020
    Abstract: A memory controller includes a mapping data controller configured to generate extended mapping data including mapping information and an additional field in response to an extended mapping data request received from a host and to generate data generation information indicating that the extended mapping data has been generated, wherein the mapping information indicates a mapping relationship between a logical block address and a physical block address and a bitmap information generator configured to receive the data generation information and generate bitmap information. The bitmap information may include information for changing a bit value corresponding to a mapping data group including the extended mapping data, among bit values included in a bitmap, to indicate the extended mapping data, and the mapping data group may include a plurality of pieces of mapping data.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventors: Eu Joon Byun, Jea Young Zhang
  • ELECTRONIC DEVICE, DATA STORAGE DEVICE, AND METHOD OF OPERATING THE SAME
    Publication number: 20210303157
    Abstract: An electronic device includes a plurality of data storage devices, each of the data storage devices including a master storage device and one or more slave storage device. Each of the plurality of data storage devices includes a storage configured to store data and a controller configured to control data input and output operations of the storage. The controller of the master storage device receives device information including storage capacity information from each of the one or more slave storage devices, selects at least one target storage device among the one or more slave storage devices upon triggering of a capacity control event, transmits source data read from the storage of the master storage device to the target storage device, and erases the source data from the storage of the master storage device.
    Type: Application
    Filed: August 19, 2020
    Publication date: September 30, 2021
    Inventor: Eu Joon BYUN
  • Data processing system and operating method thereof
    Patent number: 11119699
    Abstract: A data processing system includes a host suitable for generating a candidate logical block address (LBA) list including a plurality of candidate LBAs, a memory device suitable for storing a plurality of map segments and user data corresponding to the respective map segments, and a controller suitable for receiving the candidate LBA list from the host, and loading target map segments from the memory device, the target map segments corresponding to the plurality of candidate LBAs.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Apparatus and method to synchronize memory map between a storage device and host
    Patent number: 11119938
    Abstract: A data storage device may include: a controller, including a host memory and a device memory, configured to communicate with a host, wherein one or more host unit regions, having a first size, are allocated to the host memory; and a storage including a nonvolatile memory device. The controller may include a map data manager configured to store map data in the storage, the map data including a mapping relationship between logical addresses of the host and physical addresses of the data storage device, configured to group the logical addresses into logical address groups so that the total size of map data for each of the logical address groups corresponds to the first size, and manage a reference count for each of the logical address groups.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Memory system to perform read reclaim and garbage collection, and method of operating the same
    Patent number: 11113189
    Abstract: Provided herein is a memory system and a method of operating the same. According to the present technology, a memory system performs a garbage collection operation based on a ratio of a read count value of a memory block with reference to a read count threshold value of a read reclaim operation. Consequently, the read reclaim operation and the garbage collection operation may be prevented from overlapping with each other.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Controller and method of operating the same
    Patent number: 11113203
    Abstract: Provided herein may be a controller and a method of operating the same. The controller for controlling an operation of a semiconductor memory device may include a request analyzer, a map cache controller, and a command generator. The request analyzer receives a first request from a host. The map cache controller generates a first mapping segment including a plurality of mapping entries and a flag bit based on the first request, and sets a value of the flag bit depending on whether data corresponding to the first mapping segment is random data or sequential data. The command generator generates a program command for programming the mapping segment.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Memory system and operating method thereof
    Patent number: 11106392
    Abstract: A data processing system includes: a host suitable for generating an initialization command and generating program mode information by selecting a program mode; a memory device including a plurality of memory cells storing a single level data and a multiple-level data; and a controller suitable for: receiving the initialization command and the program mode information from the host; controlling the memory device to perform an initialization operation on the memory device in response to the initialization command; and controlling the memory device to perform a program operation on the memory device based on the program mode information after the initialization operation is performed.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
    Publication number: 20210255961
    Abstract: A memory system is provided to include a first storage device including a first memory device and a first memory controller configured to receive, from a host external to the first storage device, a request including a logical address corresponding to the request; and a second storage device including a second memory device and a second memory controller coupled to receive a request from the first storage device and to control the second memory device, wherein the first memory controller is configured to select a target address among candidate addresses and map the logical address received from the host to the target address, and wherein the candidate addresses include first physical addresses corresponding to the first memory blocks and virtual addresses corresponding to the second memory blocks included in the second memory device.
    Type: Application
    Filed: July 23, 2020
    Publication date: August 19, 2021
    Inventor: Eu Joon Byun
  • Method and system to perform urgency level garbage collection based on write history of memory blocks
    Patent number: 11086537
    Abstract: A memory system may include: a memory device including a plurality of memory blocks; and a controller configured to control the memory device, wherein the controller comprises: a block level manager configured to determine a level for each of the plurality of memory blocks based on write history of writing data to the memory device, and manage a cold block based on the level; and a garbage collection manager configured to determine a garbage collection urgent level based on a result of comparing a free block count and a first threshold value, and manage whether to perform a garbage collection operation for the cold block based on the determined garbage collection urgent level.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun