Abstract: A memory system, a memory controller and a method for operating the memory system. The memory system manages a hot data pool and a cold data pool, each of which includes at least one among a plurality of memory blocks, writes read only data to the cold data pool, and controls the hot data pool and the cold data pool in garbage collection and wear leveling, thereby classifying data, less frequently updated, into cold data and improving the performance of garbage collection and wear leveling.

Abstract: A data processing system may include: a host including a command queue including a plurality of command storage areas, and configured to store summary information of a second command among a plurality of commands in a reserved storage area of a command storage area, among the plurality of command storage areas, in which a first command among the plurality of commands being a previous command to the second command is stored, when inserting the second command into the command queue; and a data storage device configured to fetch the first command from the command queue and store the fetched first command, according to a new command notification received from the host.

Abstract: A memory system includes a memory device configured to store a piece of data in a location which is distinguished by a physical address and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to determine a timing of transferring the piece of map data into the external device to avoid decreasing an input/output throughput of the memory system.

Abstract: A memory system includes a memory device comprising a plurality of pages, and a controller suitable for storing data, inputted in response to a write command received from a host, in corresponding pages among the plurality of pages, wherein the controller generates and manages a bitmap table indicating order information of the inputted data according to the type of the write command.

Abstract: Provided herein may be a memory controller configured to control a memory device. The memory controller may include: a mapping data determination unit configured to receive, from a memory device, bitmap information indicating whether a map segment, corresponding a bit included in the bitmap information and including a plurality of pieces of extended mapping data, has been stored in the memory device and a mapping data management unit configured to output information about generation of the plurality of pieces of extended mapping data based on the bitmap information. Each of the plurality of pieces of extended mapping data may include mapping information between a logical block address and a physical block address.

Abstract: A memory controller for performing garbage collection without moving data of a valid page, controls a memory device including a plurality of memory blocks in which data is stored. The memory controller includes a victim block setting circuit for selecting a victim block among the memory blocks by receiving memory block information representing whether a valid page and an invalid page are included in each of the plurality of memory blocks, when garbage collection is performed, and a sub-block controller for outputting a sub-block read command for determining valid pages included in each of sub-blocks within the victim block, by dividing the victim block into the sub-blocks, and outputting a sub-block erase command for selectively erasing a part of the sub-blocks included in the victim block, by receiving sub-block information corresponding to the sub-block read command from the memory device.

Abstract: Various embodiments generally relate to a semiconductor device, and more particularly, to an operating method of a controller and a memory system. In accordance with an embodiment of the present disclosure, an operating method of a controller for controlling a nonvolatile memory device including a plurality of memory blocks may include: generating High Performance Booster (HPB) data based on Logical to Physical (L2P) map data and storing the HPB data into at least one empty page included in a first memory block; assigning a second memory block when a number of empty pages included in the first memory block becomes smaller than a threshold number; and migrating HPB data, which is selected according to a predetermined criterion among the HPB data stored in the first memory block, into the second memory block, wherein at least a part of the HPB data is cached into a memory of a host.

Abstract: A memory system is provided to include a first storage device including a first memory device and a first memory controller configured to receive, from a host external to the first storage device, a request including a logical address corresponding to the request; and a second storage device including a second memory device and a second memory controller coupled to receive a request from the first storage device and to control the second memory device, wherein the first memory controller is configured to select a target address among candidate addresses and map the logical address received from the host to the target address, and wherein the candidate addresses include first physical addresses corresponding to the first memory blocks and virtual addresses corresponding to the second memory blocks included in the second memory device.

Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system performs an operation of recovering system data lost due to SPO when an SPO recovery operation is performed, and flushes recovered system data into the memory device after a first time point at which the operation of recovering the system data is completed and before a second time point at which a power off preparation request is received from a host.

Abstract: A memory system may include a memory device and a controller including a memory, suitable for generating map data for mapping between a physical address corresponding to data within the memory device in response to a command and a logical address received from a host, wherein the controller selects a memory map segment among a plurality of memory map segments, when a read count corresponding to the selected memory map segment is greater than or equal to a first threshold, calculates a map miss ratio of the memory using a total read count and a map miss count, and transmits the selected memory map segment to the host when the map miss ratio is greater than or equal to a second threshold.

Abstract: A memory system may include a memory device including a plurality of dies each including a plurality of memory blocks; and a controller including a memory and a garbage collection module configured to perform a garbage collection operation by transmitting data to the memory device through at least one of a plurality of data paths, wherein the garbage collection module: determines whether the garbage collection operation is executable in parallel with a host task operation, depending on which of the plurality of dies includes a target block of the garbage collection operation.

Abstract: Embodiments of the present invention relate to a memory system, a memory device, a memory controller and an operating method thereof. A partial mapping table including some of plural pieces of mapping information between physical addresses and logical addresses, which are included in a mapping table stored in the memory device, is cached, a piece of mapping information corresponding to data indicated by a command is referred to in the partial mapping table, and whether to perform an update for a reference-related parameter of the piece of mapping information is controlled depending on a size of the data, thereby improving cache efficiency for mapping informations for processing a request from a host and through this, increasing the success rate of a cache hit.

Abstract: Provided herein may be a controller and a data storage system having the controller. The controller may include a mapping time generator configured to generate a first mapping time at which a logical block address and a physical block address are mapped to each other, an internal memory configured to store first address mapping information including an address map, and the first mapping time, a host interface configured to transmit the first address mapping information to a host, and receive second address mapping information from the host, and a central processing unit configured to generate the address map, store the first address mapping information in the internal memory, compare a second mapping time included in the second address mapping information with the first mapping time, and select a read mode based on a result of the comparison.

Abstract: Embodiments of the disclosure relate to a memory system, a memory controller and a meta-information storage device. By providing a memory device configured to store mapping information between a logical address and a physical address, a memory controller configured to control the memory device and control a memory area in which mapping segments including some of the mapping information are stored and a meta-information storage device configured to store meta-information on the memory area, it is possible to provide a memory system, a memory controller and a meta-information storage device capable of processing a command received from a host as quickly as possible even when an SPO occurs.

Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.

Abstract: A storage device includes a semiconductor memory device and a controller. The semiconductor memory device includes a plurality of memory blocks. The controller controls an operation of the semiconductor memory device. The controller includes a device garbage collection controller configured to select a victim memory block among the plurality of memory blocks, generate victim LBA information including a logical block address of a valid page in the selected victim memory block, and transfer the victim LBA information to a host device.

Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.

Abstract: Various embodiments generally relate to a semiconductor device, and more particularly, to a controller, a memory system and an operating method thereof. In accordance with an embodiment of the present disclosure, an operating method of a controller for controlling a nonvolatile memory device may include receiving a read command from a host; determining whether changed L2P map data corresponding to L2P map data included in the read command is registered in a dirty list; and performing, when the changed L2P map data is determined as registered in the dirty list, a read operation on the nonvolatile memory device based on the changed L2P map data among L2P map data included in a plurality of L2P segments.

Abstract: A method of operating a controller configured to control a semiconductor memory device including a plurality of memory blocks may include selecting victim blocks that are targets for garbage collection among the plurality of memory blocks; determining whether data stored in valid pages included in each of the victim blocks includes sequential data; and performing a garbage collection operation on the victim blocks based on whether the data stored in the valid pages included in the each of victim blocks include sequential data.

Abstract: An operation method of a memory system includes: searching for a valid physical address in memory map segments stored in the memory system, based on a read request from a host, a logical address corresponding to the read requests, and a physical address corresponding to the logical address and performing a read operation corresponding to the read request; caching some of the memory map segments in the host as host map segments based on a read count threshold indicating the number of receptions of the read request for the logical address; and adjusting the read count threshold based on a miss count indicating the number of receptions of the read request with no physical address, and a provision count indicating the number of times the memory map segment is cached in the host.