Abstract: A network on chip (NoC) response signal control apparatus and an NoC response signal control method using the apparatus are provided. The NoC response signal control apparatus includes: a network interface (NI) slave which outputs an enabling signal for a response signal via a response signal wire if a predetermined response signal is input from a slave intellectual property (IP); and an NI master which outputs a transaction to a master IP by generating the transaction for the response signal if the enabling signal is input via the response signal wire which is directly connected to the NI slave.

Abstract: An urgent packet latency control of a network on chip (NoC) apparatus and a method of urgent packet latency control of a NoC are provided. The urgent NoC packet latency control apparatus includes: an urgent packet determination unit which determines whether a packet is an urgent packet based on a predetermined field of the packet; an urgent packet path search unit which searches for at least one router, included in a routing path of the urgent packet, if the urgent packet determination unit determines that the packet is urgent; and an urgent packet path control unit which transmits output port information of the urgent packet to the router.

Abstract: Provided are an apparatus for and a method of controlling electric power of a network-on-chip (NoC). The apparatus for controlling electric power of a network-on-chip (NoC), including: a transaction monitoring unit which monitors a transaction generated from at least one of a master and a module corresponding to the master; and a clock control unit which selectively controls clock signal with respect to modules comprising the NoC, based on the monitored transaction.

Abstract: A GALS-based network-on-chip (NoC) includes a plurality of asynchronous first-in first-out (FIFO) input buffers connected to a plurality of IPs that asynchronously receive data; a plurality of asynchronous FIFO output buffers connected to the plurality of IPs asynchronously output data; and a router for forwarding data input to the plurality of asynchronous FIFO input buffers, to an asynchronous FIFO output buffer, among the plurality of asynchronous FIFO output buffers, which is connected to an IP to which the data is destined. Accordingly, the system-on-chip (SoC) adopting the GALS design scheme can transfer data via the NoC between the IPs which are in time zones having different clocks in the centralized switching system, thereby avoiding the need for a point-to-point system.

Abstract: A bus inverting code generating apparatus and a method of generating bus inverting code is provided. The bus inverting code generating apparatus includes a bit comparator comparing present input data with previous input data for each bit and outputs a bit comparison result; a bit counter counting bits of the bit comparison result and outputs a bit count result; an indicator toggling an indicator output if the bit count result that is output by the bit counter is greater than a reference value; and an inverting determiner outputting an inverting signal indicating whether the present input data is inverted based on the bit count result and the indicator output.

Abstract: An input buffer device and control method of the input buffer device. The input buffer device includes a virtual output queuing (VOQ) buffering section which has a plurality of VOQ buffers. The input buffer device stores data which is input to an input port to a VOQ buffer corresponding to an intended output port of the data among the plurality of VOQ buffers. A shared buffering section is provided which stores the data when a VOQ buffer corresponding to the intended output port of the data is full of data. The stored data is forwarded to the VOQ buffer when the VOQ buffer is empty. Accordingly, the input buffer device can more efficiently process the data by use of the fixed-length FIFO buffers and the shared buffer.

Abstract: A computer chip including a plurality of routers, each of the plurality of the routers connected to the adjacent routers in the directions of an X axis and a Y axis; and a plurality of intellectual properties, each of the plurality of the intellectual properties connected to only one of the plurality of the routers.