Abstract: An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.

Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.

Abstract: The present invention provides a snowboard binding, including a mount, rear plate, top plate assembly base, rotary top pressboard, trigger support and coupling plate. The coupling plate, the mating frame of the rotary top pressboard, the mating ends of the trigger support and the top plate assembly base are coupled together to form a four-bar mechanism. The pressing state of the rotary top pressboard can be positioned directly by the perpendicular trigger support, and the rotary top pressboard can realize an expanded opening state over 90°. Thus, the snowboard boot can be slipped directly into the snowboard binding, enabling more convenient locating and release of the snowboard binding with better efficiency and applicability.

Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.

Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.

Abstract: The invention provides systems and methods for ESD protection for an integrated circuit (IC) having multi-power domains. The IC comprises a first device in a first power domain having a first power line and a first ground line and a second device in a second power domain having a second power line and a second ground line. A clamp circuit having a first node and a second node is coupled to the first device and the second device to provide cross-domain protection. Alternatively, two clamp circuits are used to couple with the first device and the second device to provide cross-domain ESD protection.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.

Abstract: A rotary table includes a first plank which has a plurality of fastening portions and a plurality of rolling balls corresponding to fastening portions, and each fastening portion fastens each rolling ball to one side of the first plank, and a second plank which has a first baseboard, a second baseboard, an annular trough and at least one latch portion. The first baseboard and second baseboard have respectively a first trough and a second trough on one side thereof that are joined through the latch portion to form the second plank with the annular trough in a continuous manner at the same plane. The first plank is turnable relative to the second plank through the rolling balls moving in the annular trough.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: The present invention provides a snowboard binding, including a mount, rear plate, top plate assembly base, rotary top pressboard, trigger support and coupling plate. The coupling plate, the mating frame of the rotary top pressboard, the mating ends of the trigger support and the top plate assembly base are coupled together to form a four-bar mechanism. The pressing state of the rotary top pressboard can be positioned directly by the perpendicular trigger support, and the rotary top pressboard can realize an expanded opening state over 90°. Thus, the snowboard boot can be slipped directly into the snowboard binding, enabling more convenient locating and release of the snowboard binding with better efficiency and applicability.

Abstract: A detector panel having therein an X-ray detector, a signal processing circuit for interface, and a battery for power supply, the detector panel includes a first signal processing circuit for processing the detection signals from the X-ray detector, a second signal processing circuit for processing the output signal from the first signal processing circuit, a first power supply circuit for adjusting the output voltage of the battery by means of switching regulation, to supply the output to the second signal processing circuit, a second power supply circuit for adjusting the output voltage of the first power supply circuit by means of switching regulation, to supply the output to the X-ray detector and the first signal processing circuit, and a switching circuit for switching the configuration of the second power supply circuit between a single connection of one linear regulator and a series connection of two linear regulator.

Abstract: A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.

Abstract: A detector panel incorporates an X-ray detector, an electronic circuit for interface, and a battery for power supply, and also includes a measurement device for measuring the remaining power of the battery, and a determination device for determining if the operation is executable, based on the comparison between the remaining power of the battery and the threshold defined in accordance with the required power for operating the X-ray detector and the electronic circuit.