Patents by Inventor Fang Wu

Fang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230067035
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 2, 2023
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Patent number: 11549760
    Abstract: A heat dissipation assembly includes a condenser, an evaporator, a vapor conduit, and a liquid conduit. The condenser has a condensing chamber therein. Two ends of the vapor conduit are respectively connected to the condenser and the evaporator. Two ends of the liquid conduit are respectively connected to the condenser and the evaporator. A geometric center of the liquid conduit in the condensing chamber is lower than or equal to a geometric center of the condensing chamber.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: January 10, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Fang Wu, Li-Kuang Tan
  • Publication number: 20220415724
    Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.
    Type: Application
    Filed: August 4, 2021
    Publication date: December 29, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Jia Fang Wu, Hsiang-Chieh Yen, Hsu-Sheng Huang, Zhi Jian Wang
  • Patent number: 11502062
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Publication number: 20220352109
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.
    Type: Application
    Filed: August 29, 2021
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Nien-Fang Wu, Hai-Ming Chen, Yu-Min Liang, Jiun-Yi Wu
  • Patent number: 11486652
    Abstract: A heat-dissipating device includes a condenser and an evaporator. The condenser includes a shell and a main capillary wick. The shell has a chamber and a through hole communicating with the chamber. The main capillary wick is disposed in the chamber. The evaporator has an evaporating section, a gas conduit and a liquid conduit. The evaporating section has a gas cavity, and the liquid conduit communicating with the chamber and filling with a liquid. The liquid conduit having a hole communicating with the gas cavity is inserted in the gas conduit and the gas cavity. A stepped area is formed between the liquid conduit and the chamber for gathering the liquid flowing into the liquid conduit.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: November 1, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Hung Huang, Li-Kuang Tan, Wei-Fang Wu
  • Publication number: 20220315315
    Abstract: A liquid storage tank includes a housing, a piston located in the housing, a cover, an elastic element, and an outlet pipe. The cover is attached to the housing and has a support post extending toward the piston. The piston, the housing, and the cover define a tank chamber. The tank chamber is filled with cooling liquid. The elastic element is connected with the tank hosing and the piston. The elastic element is free from contact with the cooling liquid. The outlet pipe communicates with the tank chamber. An extension direction of an opening of the outlet pipe is not parallel to a direction of movement of the elastic element. When the cooling liquid is decreased, the piston compressed the tank chamber such that the elastic element is released. The tank chamber is continuously compressed by pairing the elastic element and the piston.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Inventors: Yu-Jei HUANG, Wei-Fang WU, Chia-Ying HSU, Chih-Chieh LU
  • Patent number: 11421692
    Abstract: A pump body includes a housing, a first and a second chambers separated and communicated by the housing, an input pipe communicated with the first chamber and an output pipe communicated with the second chamber. The input pipe has a water outlet located in the first chamber. The output pipe has a water inlet located in the second chamber. The first pump has a first rotor placed in the first chamber. The second pump has a second rotor placed in the second chamber, wherein an extension line of a rotating shaft of the second rotor is perpendicular to a plane where a rotating shaft of the first rotor located.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 23, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Fang Wu, Chia-Ying Hsu, Chia-Yu Yeh, Chi-Chang Teng
  • Publication number: 20220189918
    Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20220181301
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 9, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20220168215
    Abstract: A composition with exogenous mitochondria as active ingredients, and a use thereof and a cell repairing method therefor. The composition includes exogenous mitochondria and at least one pharmaceutically or cosmetically acceptable carrier. The composition may further include an adjuvant, and the adjuvant is selected from a group consisting of serum, plasma, complement and at least the above two ingredients. The exogenous mitochondria are obtained from cells by a centrifugal purification method.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Applicant: TAIWAN MITOCHONDRION APPLIED TECHNOLOGY CO., LTD.
    Inventors: Hong-Lin SU, Hsueh-Min TSENG, Shih-Fang WU
  • Patent number: 11322477
    Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20220120510
    Abstract: A heat dissipation assembly includes a condenser, an evaporator, a vapor conduit, and a liquid conduit. The condenser has a condensing chamber therein. Two ends of the vapor conduit are respectively connected to the condenser and the evaporator. Two ends of the liquid conduit are respectively connected to the condenser and the evaporator. A geometric center of the liquid conduit in the condensing chamber is lower than or equal to a geometric center of the condensing chamber.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Inventors: Wei-Fang WU, Li-Kuang TAN
  • Patent number: 11291298
    Abstract: The present invention has a lifting table, comprising an upper platform, a lower platform, and at least one group of lifting component positioned between the upper and lower platforms and used for adjusting the height of the upper platform relative to the lower platform; the lifting table further comprises elastic elements and sliding components sliding fit on the upper or lower platform; the sliding components are connected with the elastic elements for sliding on the upper or lower platform under the effect of elastic forces from the elastic elements; each sliding component has a push part, the lifting component exerts an acting force to the push part so that the sliding component overcomes the elastic force of the elastic element to slide along the upper or lower platform, and is simple and labor-saving in operation and good in user experience.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: April 5, 2022
    Assignee: LOCTEK ERGONOMIC TECHNOLOGY CORP.
    Inventors: Lehong Xiang, Tao Lin, Fang Wu
  • Publication number: 20220098568
    Abstract: The present invention provides histidyl-tRNA synthetase and Fc region conjugate polypeptides (HRS-Fc conjugates), such as HRS-Fc fusion polypeptides, compositions comprising the same, and methods of using such conjugates and compositions for treating or diagnosing a variety of conditions. The HRS-Fc conjugates of the invention have improved controlled release properties, stability, half-life, and other pharmacokinetic and biological properties relative to corresponding, unmodified HRS polypeptides.
    Type: Application
    Filed: June 10, 2021
    Publication date: March 31, 2022
    Inventors: Chi-Fang WU, Darin LEE, Jeffry D. WATKINS, Kristi PIEHL, Kyle CHIANG, Marc THOMAS, Minh-Ha DO, Ying BUECHLER, John D. MENDLEIN
  • Patent number: 11264362
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Patent number: 11236948
    Abstract: A heat dissipation assembly includes a condenser, an evaporator, a vapor conduit, and a liquid conduit. The condenser has a condensing chamber therein. Two ends of the vapor conduit are respectively connected to the condenser and the evaporator. Two ends of the liquid conduit are respectively connected to the condenser and the evaporator. A geometric center of the liquid conduit in the condensing chamber is lower than or equal to a geometric center of the condensing chamber.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: February 1, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Fang Wu, Li-Kuang Tan
  • Patent number: D957700
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: July 12, 2022
    Inventor: Fang Wu
  • Patent number: D957701
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: July 12, 2022
    Inventor: Fang Wu
  • Patent number: D957702
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: July 12, 2022
    Inventor: Fang Wu