Abstract: An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.

Abstract: A comparison method compares the address of a memory cell with a known address of a faulty memory cell in a semiconductor memory module. The module is subdivided into banks and has an address structure in which each address is associated with a bank that is organized in rows and columns and is defined by a row address, a column address and a bank address. Not only the row address is determined, but also the column address and the bank address when a memory access occurs. A bank is activated with a bank selection signal, and the access to a valid address of a faulty memory cell is indicated by an enable register.

Abstract: A circuit configuration for driving a programmable link, for example a fuse, is specified, having a drive circuit for driving the fuse in a manner dependent on a signal present at the data input, and also a volatile memory, whose output is preferably directly connected to the data input of the drive circuit. A circuit configuration for particularly fast and simple programming of fuses, in particular electrically programmable fuses, is thereby specified.

Abstract: An integrated circuit includes a self-test device which is provided for executing a self-test of the integrated circuit and which has a control output. A program memory is connected to the self-test device for storing at least one test program supplied from outside the integrated circuit. The test program is run by the self-test device during execution of a self-test. The self-test device controls loading of a respective test program to be run into the program memory from outside the integrated circuit through the control output thereof.

Abstract: A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a clock pulse with respect to the operating clock of the other, second memory bank. Partial data streams are combined at the output of the two memory banks to form a data stream with double the frequency.

Abstract: The invention relates to a semiconductor module having a plurality of signal paths for carrying external signals that each contain a setup and hold circuit on the basis of a latch circuit with a full latch and a logic circuit. The latch circuit contains at a beginning of the signal path upstream of the logic circuit a hold latch. The hold latch responds to the leading edge of a fast clock signal derived from the clock signal of the external signal, for the early latching of the external signal and for the decoupling of the hold time from the setup time. The full latch is disposed downstream of the logic circuit for the final latching of the external signal or of a signal derived from the latter.

Abstract: A vertical MOS field effect transistor includes a gate disposed in a trench, a channel, and a source and a drain disposed in the substrate on the trench wall. The gate annularly surrounds a drain terminal which extends from the substrate surface as far as the drain disposed on the trench bottom. It is possible to produce vertical transistors with different channel lengths on a substrate with trenches of different widths by employing oblique implantation when producing the gate. A method of producing the vertical field effect transistor is also provided.

Abstract: In the configuration, the module can “learn” one or more time intervals from the external tester and then repeat them internally or compare them to its own internally measured time intervals, for instance, for the purpose of evaluating whether the module in question has crossed a time specification value or remains below the value. The module can also measure and store one or more internal time intervals and transmit them to the external tester in digital or analog form.

Abstract: A circuit configuration for driving a programmable link, for example a fuse, is specified, having a drive circuit for driving the fuse in a manner dependent on a signal present at the data input, and also a volatile memory, whose output is preferably directly connected to the data input of the drive circuit. A circuit configuration for particularly fast and simple programming of fuses, in particular electrically programmable fuses, is thereby specified.

Abstract: A circuit configuration for driving a programmable link has a drive circuit for the selection and blowing of the fuse, and also a shift register, by which an activation signal can be fed to the drive circuit. In order to provide the data to be blown, in a preferred embodiment, a volatile memory cell may be provided. The present circuit configuration enables the blowing of fuses and thus repair of defective memory cells in mass memories even after encapsulation of a chip having the mass memory. Moreover, the shift register described effectively prevents impermissibly high currents from being able to occur as a result of simultaneous blowing of too many fuses.

Abstract: A circuit configuration is provided for level boosting, in particular for driving a link that can be programmed by an energy pulse, which is also referred to as a fuse. The circuit configuration has a circuit for level boosting and also a logic circuit. The logic circuit combines a first input signal with a second input signal and controls an input of the circuit for level boosting, the output level of an output signal of the circuit for level boosting being greater than the input level. A fusible link can be connected to an output terminal of the circuit for level boosting. Since an input stage of the circuit for level boosting is at the same time a first subcircuit of the logic circuit, the circuit configuration enables an exceptional component and area-saving construction. This has an advantageous effect particularly in mass memory chips.

Abstract: A circuit configuration for driving a programmable link has a volatile memory cell, which is coupled to the fuse for the permanent storage of data stored in the volatile memory, and also a shift register, which enables data to be read out from the volatile memory cell and data to be written to the memory cell. In this case, a plurality of shift registers may be interconnected to form a shift register chain for the purpose of driving a plurality of fuses. The shift register chain thus enables fast writing and reading to/from the volatile memory with a low outlay on circuitry.

Abstract: A self-test device serves for carrying out a self-test of an integrated circuit. An output of the self-test device is connected to a contact-making point of the circuit, which serves for external contact-making and which is connected to an input of a circuit unit of the integrated circuit to be tested. The self-test device feeds a test signal through the contact-making point to the circuit unit.

Abstract: An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.

Abstract: The memory device of a semiconductor chip is tested with a BIST circuit. The configuration and the method store the test results obtained by the BIST circuit. The test results are stored in the sense amplifiers of the memory device. In addition, it also possible for test programs for the BIST circuit to be stored in the sense amplifiers.

Abstract: An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity type. The well is electrically insulated from the substrate. The semiconductor circuit furthermore contains a control circuit with a variable output signal. The well terminal of the transistor is connected to the output signal of the control circuit. The transistor is protected against permanent damage by virtue of its well potential being raised in a corresponding operating mode of the semiconductor circuit in which an increased operating voltage is applied to the transistor.

Abstract: The invention relates to a system and to a method for repairing bit errors in memory chips having a multiplicity of memory cells, in which a bit error is detected using an error identification algorithm, the address of the faulty memory cell is determined and the fault is repaired by activating a redundant memory cell, with the repair being effected in the memory chip's finally installed state with the end user.

Abstract: An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity type. The well is electrically insulated from the substrate. The semiconductor circuit furthermore contains a control circuit with a variable output signal. The well terminal of the transistor is connected to the output signal of the control circuit. The transistor is protected against permanent damage by virtue of its well potential being raised in a corresponding operating mode of the semiconductor circuit in which an increased operating voltage is applied to the transistor.

Abstract: A method for supplying current to a semiconductor chip, particularly to a semiconductor memory chip, in which, in a standby mode, the semiconductor chip is supplied with current from a standby current generator, and in which, in a normal operating mode, the semiconductor chip is supplied with current from a normal mode current generator. The standby current generator provides a smaller current than the normal mode current generator, and where, in a product development phase, the semiconductor chip is supplied with current from the standby current generator in a test mode. The semiconductor chip is additionally to be supplied with current from the normal mode current generator in the product development phase.

Abstract: A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.