Abstract: In order to identify an integrated circuit, the bits of the chip ID are programmed by fuses or antifuses. Programming errors and aging errors can be detected and corrected by adding redundant bits. This can be applied in particular when electrically programmable fuses/antifuses are used in order to make the re-detection of a faulty chip ID more reliable.

Abstract: The invention relates to a semiconductor module having a plurality of signal paths for carrying external signals that each contain a setup and hold circuit on the basis of a latch circuit with a full latch and a logic circuit. The latch circuit contains at a beginning of the signal path upstream of the logic circuit a hold latch. The hold latch responds to the leading edge of a fast clock signal derived from the clock signal of the external signal, for the early latching of the external signal and for the decoupling of the hold time from the setup time. The full latch is disposed downstream of the logic circuit for the final latching of the external signal or of a signal derived from the latter.

Abstract: A method and a memory system temporarily store the addresses in a memory field during the writing-in of data. The addresses are applied to a write unit simultaneously with the data. Due to the intermediate storage of the addresses, the data can be input in a flexible manner, for example, even with a chronological delay in relation to the addresses.

Abstract: In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

Abstract: An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity type. The well is electrically insulated from the substrate. The semiconductor circuit furthermore contains a control circuit with a variable output signal. The well terminal of the transistor is connected to the output signal of the control circuit. The transistor is protected against permanent damage by virtue of its well potential being raised in a corresponding operating mode of the semiconductor circuit in which an increased operating voltage is applied to the transistor.

Abstract: The semiconductor component is provided for connection to a test system. An external clock signal with a modulated duty ratio can be input to the semiconductor component at a connection provided for that purpose on the semiconductor component. The latter has a clock recovery circuit, which obtains a periodic clock signal from the modulated clock signal, and a shift register, to which the modulated clock signal can be fed in a manner clocked by the periodic clock signal and which provides a data signal. The present invention makes it possible, in particular in mass memory chips, to feed in clock signals and also program, address or data signals for the realization of BIST via just one connection contact.

Abstract: The memory cells of an integrated memory are successively tested and immediately following the detection of a defect of the memory cell currently being tested, the affected row line or column line is replaced by programming one of the redundant lines. After a certain number of the redundant lines have been programmed, the programming of at least one of the redundant lines is canceled if a further defect is found. This redundant line is programmed for repairing a defect of another memory cell.

Abstract: An integrated circuit incorporating a self-test device and a method for producing a self-testing integrated circuit. The integrated circuit has a program memory with at least one external terminal for loading external test programs. The integrated circuit has a self-test device connected to the program memory, the self-test device executing program commands of a test program loaded into the program memory, the program commands succeeding one another in address terms, for carrying out a self-test of the circuit. The self-test device has an interrupt signal input, through which the self-test device interrupts the test program that is currently being executed by not executing the respective succeeding program command in address terms. Rather, it executes a program jump within the test program, the program jump being triggered by the interrupt signal.

Abstract: An integrated circuit includes a data processing unit, a buffer memory, and a setting memory. The buffer memory performs the function of registers for storing data for the processing unit. The buffer memory is connected to the setting memory. The setting memory can be written to through the buffer memory.

Abstract: A circuit includes a programmable element having conductor track resistance that can be permanently altered by an electric current. The circuit also has a switchable element for receiving a control signal for programming the programmable element. The programmable element and the switchable element are connected in series between two supply potentials. The programmable element can have an electrical fuse. The input of a read-out circuit is connected through a protective circuit to the circuit node between the programmable element and the switchable element. The protective circuit serves for limiting the voltage potential at the input of the read-out circuit during a programming operation. The circuit elements of the read-out circuit can thus be dimensioned in an area-saving manner. The protective circuit also can include a diode having an anode connected to the input of the read-out circuit and a cathode connected to a third supply potential.

Abstract: A circuit configuration has a switchable element for programming a programmable element whose conductor track resistance can be permanently altered by an electric current or an electric voltage. The programmable element and the switchable element are connected in series and are connected to a first supply potential and a second supply potential, respectively. A monitoring circuit is connected in series with a series circuit formed by the programmable element and the switchable element between the terminals for the first and the second supply potential. The monitoring circuit measures an electrical parameter which is characteristic of a programming operation. Thus, it is possible to monitor the burning operation of the electrically programmable element during the programming operation.

Abstract: In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

Abstract: A method provides that, when a driver circuit is deactivated, a first capacitor disposed at an output of the driver circuit is placed at a first potential. The driver circuit is then activated at a first point in time, so that a current flows between its output and the first capacitor. The flow of current between the output of the driver circuit and the first capacitor is interrupted at a second point in time and the potential at the first capacitor is subsequently determined as a measure of the drive capability of the driver circuit.

Abstract: A method of testing leakage current at a contact-making point in an integrated circuit includes applying a test potential to the contact-making point through an output of an application device. The output of the application device is connected to a high impedance or is isolated from the contact-making point. The potential at the contact-making point is determined as a measure of the leakage current being produced.

Abstract: At least two different submethods for repairing defective memory cells are used sequentially. In the submethods, the memory cells are successively tested in each case, and, directly after a defect has been ascertained, the relevant row line or the relevant column line is replaced by programming one of the redundant lines. The submethods differ in terms of their repair strategy. One submethod is called with a defect-signature which terminates the submethod and contains information about the number of checked memory cells and the repair result. Subsequently, depending on the defect-signature of the preceding submethod, another submethod is called, which initially does not cancel, partially cancels, or entirely cancels, the programming that has been performed.

Abstract: A circuit configuration has memory devices, each containing a programmable element and a volatile memory element. For each of the memory devices, the programmable element is connected to the volatile memory element to store a state of the programmable element in the volatile memory element. A respective memory device has at least one output for checking the respective state of the programmable element in the associated volatile memory element. The memory devices can be addressed individually via a selection circuit to output the states of the programmable element and of the volatile memory element. The information stored in the volatile memory element is retained in this process.

Abstract: In a module with a BIST function to which signal pulses are fed from outside with a tester, a configuration for generating signal impulses of defined lengths includes registers configured to store measured pulse lengths, and a variable delay element configured to measure pulse lengths of externally supplied signal pulses in a training phase. The element has a series circuit of inverters and delay-free signal paths parallel thereto for read/write from/into the registers. AND gates are disposed between a delay-free write signal path and the element and behind an even number of respective inverters, and the output of the AND gates are connected to the registers through the decoder. AND gates are disposed between the delay-free read signal path and the element and behind an even number of respective inverters. One input of the AND gates is connected to the registers through the decoder, another input is connected to the element, and the outputs are connected to the delay-free read signal path.

Abstract: The memory cells of an integrated memory are successively tested and immediately following the detection of a defect of the memory cell currently being tested, the affected row line or column line is replaced by programming one of the redundant lines. After a certain number of the redundant lines have been programmed, the programming of at least one of the redundant lines is canceled if a further defect is found. This redundant line is programmed for repairing a defect of another memory cell.

Abstract: An integrated circuit includes a self-test device which is provided for executing a self-test of the integrated circuit and which has a control output. A program memory is connected to the self-test device for storing at least one test program supplied from outside the integrated circuit. The test program is run by the self-test device during execution of a self-test. The self-test device controls loading of a respective test program to be run into the program memory from outside the integrated circuit through the control output thereof.

Abstract: A bonding pad test configuration for establishing whether or not a semiconductor chip is bonded. The test configuration has a circuit that evaluates a state of a bond between a bonding wire and the bonding pad and is able to activate and deactivate operating and test modes depending on the bond state established. To this end, the bonding pad is divided into at least two parts, so that the circuit produced in the semiconductor chip itself can use signals derived from the parts of the bonding pad to establish whether or not the bonding wire is in contact with the parts.