Abstract: A semiconductor device includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed on a first surface of the base substrate, and a second type III-V semiconductor layer with a different bandgap as the first type III-V being formed on the first type III-V semiconductor layer. The semiconductor device further includes first and second electrically conductive device terminals each being formed on the second type III-V semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas. The base substrate includes a first highly doped island that is disposed directly beneath the second device terminal and extends to the first surface of the base substrate. The first highly-doped island is laterally disposed between portions of semiconductor material having a lower net doping concentration than the first highly-doped island.

Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on th

Abstract: The invention relates to a deep depletion MIS transistor (100), comprising: a source region (S) and a drain region (D) made of doped semiconductor diamond of a first conductivity type; a channel region (C) made of doped semiconductor diamond of the first conductivity type, arranged between the source region and the drain region; a drift region (DR) made of doped semiconductor diamond of the first conductivity type, arranged between the channel region and the drain region; and a conductive gate (111) arranged on the channel region and separated from the channel region by a dielectric layer (113).

Abstract: A fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising: a semiconductor substrate comprising a first etched portion and a second etched portion; a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises a first dielectric membrane located over the first etched portion of the semiconductor substrate, and a second dielectric membrane located over the second etched portion of the semiconductor substrate; two temperature sensing elements on or within the first dielectric membrane and two temperature sensing elements on or within the second dielectric membrane; an output circuit configured to measure a differential signal between the two temperature sensing elements of the first dielectric membrane and the two temperature sensing elements of the second dielectric membrane; wherein the first dielectric membrane is exposed to the fluid and the second dielectric membrane is isolated from the fluid.

Abstract: An insulated gate bipolar transistor includes a source electrode, a collector electrode, a source layer, a base layer, a drift layer and a collector layer. Trench gate electrodes extend through the base layer into the drift layer. A channel is located between the source layer, the base layer and the drift layer. A trench Schottky electrode is adjacent to one of the trench gate electrodes and includes an electrically conductive Schottky layer arranged lateral to the base layer and extends through the base layer into the drift layer. The Schottky layer is electrically connected to the source electrode. Collection areas are located in the drift layer at a respective trench gate electrode bottom of the trench gate electrodes or of the trench Schottky electrode. The Schottky layer forms a Schottky contact to the collection area at a contact area.

Abstract: We disclose herein a flow and thermal conductivity sensor comprising a semiconductor substrate comprising an etched portion, a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises at least one dielectric membrane located over the etched portion of the semiconductor substrate and a heating element located within the dielectric membrane. The dielectric membrane comprises one or more discontinuities located between the heating element and an edge of the dielectric membrane.

Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate (4) and a second heterojunction transistor formed on the substrate. The first heterojunction transistor comprises: first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal (8) operatively connected to the first III-nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; and a first gate region (10) over the first III-nitride semiconductor region between the first and second terminals.

Abstract: We disclose herein a sensing device comprising a semiconductor substrate having a first etched portion, a dielectric layer located on or over the semiconductor substrate, wherein the dielectric layer comprises a first dielectric membrane located adjacent to the first etched portion of the semiconductor substrate, a pressure sensing element and/or a flow sensing element within the first dielectric membrane, and a first structure configured to reinforce the dielectric membrane. A first portion of the first structure is located within the first dielectric membrane, the first structure has a higher stiffness than the first dielectric membrane, and the first portion of the first structure is located between a perimeter of the dielectric membrane and the pressure sensing element or flow sensing element.

Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: We disclose a Ill-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor (19) formed on a substrate, the first heterojunction transistor comprising: a first Ill-nitride semiconductor region formed over the substrate, wherein the first Ill-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal (8) operatively connected to the first Ill-nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first Ill-nitride semiconductor region; a first gate terminal (10) formed over the first Ill-nitride semiconductor region between the first terminal and the second terminal.

Abstract: A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.

Abstract: We disclose herein a fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising a semiconductor substrate comprising a first etched portion, a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises a first dielectric membrane located over the first etched portion of the semiconductor substrate, a heating element located within the first dielectric membrane, and a first temperature sensing element spatially separated from the heating element. The fluid sensor further comprises a second temperature sensing element within the dielectric membrane, or the heating element may be further configured to operate as a second temperature sensing element.

Abstract: A fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising: a semiconductor substrate comprising a first etched portion; a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises a first dielectric membrane located over the first etched portion of the semiconductor substrate; a first heating element located within the first dielectric membrane; and a second heating element; wherein the first heating element is arranged to thermally shield the second heating element from ambient temperature changes; wherein the first heating element or the second heating element is configured to operate as a temperature sensing element; wherein the first heating element is configured to operate in a constant temperature or constant resistance mode; wherein the second heating element is configured to operate in a constant current or constant voltage mode or constant power mode; and wherein the sensor is configured to determine a thermal conductivity of t

Abstract: We disclose herein a flow sensor assembly comprising a first substrate, a flow sensor located over the first substrate, a lid located over the flow sensor, a flow inlet channel, and a flow outlet channel. A surface of the flow sensor and a surface of the lid cooperate to form a flow sensing channel between the flow inlet channel and the flow outlet channel, and a surface of the flow sensing channel is substantially flat throughout the length of the flow sensing channel.

Abstract: The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.

Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary gate terminal (15) and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device (205) and a low-voltage auxiliary GaN device (210) wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: A heterojunction device, includes a substrate; a III-nitride semiconductor region located longitudinally above or over the substrate and including a heterojunction having a two-dimensional carrier gas; first and second laterally spaced terminals operatively connected to the semiconductor; a gate structure of first conductivity type located above or longitudinally over the semiconductor region and laterally spaced between the first and second terminals; a control gate terminal operatively connected to the gate structure, a potential applied to the control gate terminal modulates and controls a current flow through the carrier gas between the terminals, the carrier gas being a second conductivity type; an injector of carriers of the first conductivity type laterally spaced away from the second terminal; and a floating contact layer located over the carrier gas and laterally spaced away from the second terminal and operatively connected to the injector and the semiconductor region.

Abstract: Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: We disclose herein a depletion mode III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and a gate terminal formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension.

Abstract: We disclose herein a flow and thermal conductivity sensor comprising a semiconductor substrate comprising an etched portion, a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises at least one dielectric membrane located over the etched portion of the semiconductor substrate and a heating element located within the dielectric membrane. The dielectric membrane comprises one or more discontinuities located between the heating element and an edge of the dielectric membrane.