Patents by Inventor Florin Udrea

Florin Udrea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157979
    Abstract: We disclose a high voltage semiconductor device comprising a semiconductor substrate of a second conductivity type; a semiconductor drift region of the second conductivity type disposed over the semiconductor substrate, the semiconductor substrate region having higher doping concentration than the drift region; a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on the surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from a surface of the device.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: December 18, 2018
    Assignee: Anvil Semiconductors Limited
    Inventors: Peter Ward, Neophytos Lophitis, Tanya Trajkovic, Florin Udrea
  • Patent number: 10128302
    Abstract: We disclose herein a thermal IR detector array device comprising a dielectric membrane, supported by a substrate, the membrane having an array of IR detectors, where the array size is at least 3 by 3 or larger, and there are tracks embedded within the membrane layers to separate each element of the array, the tracks also acting as heatsinks and/or cold junction regions.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: November 13, 2018
    Assignee: AMS SENSORS UK LIMITED
    Inventors: Florin Udrea, Syed Zeeshan Ali, Richard Henry Hopper, Julian Gardner, Andrea De Luca
  • Patent number: 10115812
    Abstract: A semiconductor device includes a drift region of a first conductivity type, an anode region of a second conductivity type situated below the drift region, an inversion region of the second conductivity type situated above the drift region, an enhancement region of the first conductivity type situated between the drift region and the inversion region, first and second control trenches extending through the inversion region and the enhancement region into the drift region, each control trench being bordered by a cathode diffusion region of the first conductivity type, and a superjunction structure situated in the drift region between the first and the second control trenches so that the superjunction structure does not extend under either the first or the second control trench. The superjunction structure is separated from the inversion region by the enhancement region and includes alternating regions of the first and the second conductivity types.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 30, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
  • Publication number: 20180269282
    Abstract: A semiconductor device includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed on a first surface of the base substrate, and a second type III-V semiconductor layer with a different bandgap as the first type III-V being formed on the first type III-V semiconductor layer. The semiconductor device further includes first and second electrically conductive device terminals each being formed on the second type III-V semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas. The base substrate includes a first highly doped island that is disposed directly beneath the second device terminal and extends to the first surface of the base substrate. The first highly-doped island is laterally disposed between portions of semiconductor material having a lower net doping concentration than the first highly-doped island.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 20, 2018
    Inventors: Shu Yang, Giorgia Longobardi, Florin Udrea, Dario Pagnano, Gianluca Camuso, Jinming Sun, Mohamed Imam, Alain Charles
  • Patent number: 9871128
    Abstract: There are disclosed herein various implementations of a bipolar semiconductor device with sub-cathode enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite the first conductivity type. The bipolar semiconductor device also includes first and second depletion trenches, each having a depletion electrode. In addition, the bipolar semiconductor device includes a first control trench situated between the first and second depletion trenches, the first control trench extending into the drift region and being adjacent to cathode diffusions. An enhancement region having the first conductivity type is localized in the drift region between the first control trench and one or both of the first and second depletion trenches. In one implementation, the bipolar semiconductor device may be an insulated-gate bipolar transistor (IGBT).
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 16, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Gianluca Camuso, Alice Pei-Shan Hsieh, Chiu Ng, Yi Tang, Rajeev Krishna Vytla, Canhua Li
  • Publication number: 20180012983
    Abstract: A semiconductor device includes a drift region of a first conductivity type, an anode region of a second conductivity type situated below the drift region, an inversion region of the second conductivity type situated above the drift region, an enhancement region of the first conductivity type situated between the drift region and the inversion region, first and second control trenches extending through the inversion region and the enhancement region into the drift region, each control trench being bordered by a cathode diffusion region of the first conductivity type, and a superjunction structure situated in the drift region between the first and the second control trenches so that the superjunction structure does not extend under either the first or the second control trench. The superjunction structure is separated from the inversion region by the enhancement region and includes alternating regions of the first and the second conductivity types.
    Type: Application
    Filed: September 1, 2017
    Publication date: January 11, 2018
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
  • Patent number: 9859360
    Abstract: A termination region of an IGBT is described, in which surface p-rings are combined with oxide/polysilicon-filled trenches, buried p-rings and surface field plates, so as to obtain an improved distribution of potential field lines in the termination region. The combination of surface ring termination and deep ring termination offers a significant reduction in the amount silicon area which is required for the termination region.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 2, 2018
    Assignee: ABB Schweiz AG
    Inventors: Marina Antoniou, Florin Udrea, Iulian Nistor, Munaf Rahimo, Chiara Corvasce
  • Publication number: 20170363589
    Abstract: A thermal conductivity sensing device (1) is disclosed, along with a method for operation of the thermal conductivity sensing device and use of the thermal conductivity sensing device in a system for gas chromatography and a method of carrying out gas chromatography. The thermal conductivity sensing device is for use in sensing one or more gaseous components in a flowing gaseous environment. The device has a first sensor (4B) and a second sensor (4A) for exposure to the same flowing gaseous environment (G). The first sensor has an associated flow altering means (20) to affect gas flow at least at part of the surface of the first sensor, to be different to gas flow at the surface of the second sensor. Each sensor provides an output relating to heat transfer between a surface of the sensor and the gaseous environment. The device is operable to compare outputs of the first and second sensors. The sensor is able to reduce the effects of bulk convection of the flowing gas on thermal conductivity measurements.
    Type: Application
    Filed: November 27, 2015
    Publication date: December 21, 2017
    Inventors: Vasant Ramachandran Kumar, Sohab Sarfraz, Florin Udrea
  • Publication number: 20170343502
    Abstract: We disclose herein an environmental sensor system comprising an environmental sensor comprising a first heater and a second heater in which the first heater is configured to consume a lower power compared to the second heater. The system also comprises a controller coupled with the environmental sensor. The controller is configured to detect if a measured value of a targeted environmental parameter is present. The controller is configured to switch on at least one of the first and second heaters based on the presence and/or result of the measured value of the targeted environmental parameter.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Syed Zeeshan Ali, Simon Jonathan Stacey, Florin Udrea
  • Publication number: 20170343500
    Abstract: We disclose a micro-hotplate comprising a substrate comprising an etched portion and a substrate portion and a dielectric region over the substrate. The dielectric region comprises first and second portions. The first portion is adjacent to the etched portion of the substrate and the second portion is adjacent to the substrate portion of the substrate. The micro-hotplate further comprises a heater formed in the dielectric region, and a ring structure formed within and/or over the dielectric region such that the ring structure is coupled with the first and second portions of the dielectric region.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Florin Udrea, Syed Zeeshan Ali, Mohamed Foysol Chowdhury
  • Patent number: 9831330
    Abstract: There are disclosed herein various implementations of a bipolar semiconductor device having a deep charge-balanced structure. Such a device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type. The device also includes a control trench extending through an inversion region having the second conductivity type into the drift region, and bordered by a cathode diffusion having the first conductivity type. In addition, the device includes a deep sub-trench structure situated under the control trench. The deep sub-trench structure includes one or more first conductivity regions having the first conductivity type and one or more second conductivity region having the second conductivity type, the one or more first conductivity regions and the one or more second conductivity regions configured to substantially charge-balance the deep sub-trench structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: November 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
  • Patent number: 9799725
    Abstract: There are disclosed herein various implementations of an insulated-gate bipolar transistor (IGBT) having a deep superjunction structure. Such an IGBT includes a drift region having a first conductivity type situated over a collector having a second conductivity type. The IGBT also includes a gate trench extending through a base having the second conductivity type into the drift region. In addition, the IGBT includes a deep superjunction structure situated under the gate trench. The deep superjunction structure includes one or more first conductivity regions having the first conductivity type and two or more second conductivity region having the second conductivity type, the one or more first conductivity regions and the two or more second conductivity regions configured to substantially charge-balance the deep superjunction structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
  • Publication number: 20170271487
    Abstract: There are disclosed herein various implementations of a bipolar semiconductor device with sub-cathode enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite the first conductivity type. The bipolar semiconductor device also includes first and second depletion trenches, each having a depletion electrode. In addition, the bipolar semiconductor device includes a first control trench situated between the first and second depletion trenches, the first control trench extending into the drift region and being adjacent to cathode diffusions. An enhancement region having the first conductivity type is localized in the drift region between the first control trench and one or both of the first and second depletion trenches. In one implementation, the bipolar semiconductor device may be an insulated-gate bipolar transistor (IGBT).
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Florin Udrea, Gianluca Camuso, Alice Pei-Shan Hsieh, Chiu Ng, Yi Tang, Rajeev Krishna Vytla, Canhua Li
  • Publication number: 20170271488
    Abstract: There are disclosed herein various implementations of a bipolar semiconductor device with multi-trench enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having an opposite, second conductivity type. The device also includes a first control trench extending through an inversion region having the second conductivity type, and further extending into the drift region, the first control trench being adjacent to cathode diffusions. In addition, the device includes first and second depletion trenches, each having a depletion electrode, the first depletion trench being situated between the second depletion trench and the first control trench. An enhancement region having the first conductivity type is localized in the drift region and extends from the first control trench to the first second depletion trench and further from the first depletion trench to the second depletion trench.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Florin Udrea, Gianluca Camuso, Alice Pei-Shan Hsieh, Chiu Ng, Yi Tang, Rajeev Krishna Vytla, Canhua Li
  • Publication number: 20170271445
    Abstract: There are disclosed herein various implementations of a bipolar semiconductor device having localized enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite the first conductivity type. The bipolar semiconductor device also includes a first control trench extending through an inversion region having the second conductivity type, and further extending into the drift region, the first control trench being adjacent to cathode diffusions. In addition, the bipolar semiconductor device includes first and second depletion trenches, each having a depletion electrode, the first depletion trench being situated between the second depletion trench and the first control trench. An enhancement region having the first conductivity type is localized in the drift region between the first and second depletion trenches.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Florin Udrea, Gianluca Camuso, Alice Pei-Shan Hsieh, Chiu Ng, Yi Tang, Rajeev Krishna Vytla, Canhua Li
  • Patent number: 9768284
    Abstract: There are disclosed herein various implementations of a bipolar semiconductor device having a charge-balanced inter-trench structure. Such a device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type. The device also includes first and second control trenches extending through an inversion region having the second conductivity type into the drift region, each of the first and second control trenches being bordered by a cathode diffusion having the first conductivity type. In addition, the device includes an inter-trench structure situated in the drift region between the first and second control trenches.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
  • Publication number: 20170243937
    Abstract: We disclose a high voltage semiconductor device comprising a semiconductor substrate of a second conductivity type; a semiconductor drift region of the second conductivity type disposed over the semiconductor substrate, the semiconductor substrate region having higher doping concentration than the drift region; a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on the surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from a surface of the device.
    Type: Application
    Filed: September 17, 2015
    Publication date: August 24, 2017
    Inventors: Peter Ward, Neophytos Lophitis, Tanya Trajkovic, Florin Udrea
  • Publication number: 20170219434
    Abstract: We disclose an array of Infra-Red (IR) detectors comprising at least one dielectric membrane formed on a semiconductor substrate comprising an etched portion; at least two IR detectors, and at least one patterned layer formed within or on one or both sides of the said dielectric membrane for controlling the IR absorption of at least one of the IR detectors. The patterned layer comprises laterally spaced structures.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Florin Udrea, Syed Zeeshan Ali, Richard Henry Hopper, Julian Gardner, Andrea De Luca
  • Publication number: 20170221959
    Abstract: We disclose herein a thermal IR detector array device comprising a dielectric membrane, supported by a substrate, the membrane having an array of IR detectors, where the array size is at least 3 by 3 or larger, and there are tracks embedded within the membrane layers to separate each element of the array, the tracks also acting as heatsinks and/or cold junction regions.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Florin Udrea, Syed Zeeshan Ali, Richard Henry Hopper, Julian Gardner, Andrea De Luca
  • Patent number: 9685506
    Abstract: There are disclosed herein implementations of an insulated-gate bipolar transistor (IGBT) having an inter-trench superjunction structure. Such an IGBT includes a drift region having a first conductivity type situated over a collector having a second conductivity type. The IGBT also includes first and second gate trenches extending through a base having the second conductivity type into the drift region, the first and second gate trenches each being bordered by an emitter diffusion having the first conductivity type. In addition, the IGBT includes an inter-trench superjunction structure situated in the drift region between the first and second gate trenches.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: June 20, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla