Abstract: We disclose herewith a heterostructure-based sensor comprising a substrate comprising an etched portion and a substrate portion; a device region located on the etched portion and the substrate portion; the device region comprising at least one membrane region which is an area over the etched portion of the substrate. At least one heterostructure-based element is located at least partially within or on the at least one membrane region, the heterostructure-based element comprising at least one two dimensional (2D) carrier gas.

Abstract: A heterojunction device, includes a substrate; a III-nitride semiconductor region located longitudinally above or over the substrate and including a heterojunction having a two-dimensional carrier gas; first and second laterally spaced terminals operatively connected to the semiconductor; a gate structure of first conductivity type located above or longitudinally over the semiconductor region and laterally spaced between the first and second terminals; a control gate terminal operatively connected to the gate structure, a potential applied to the control gate terminal modulates and controls a current flow through the carrier gas between the terminals, the carrier gas being a second conductivity type; an injector of carriers of the first conductivity type laterally spaced away from the second terminal; and a floating contact layer located over the carrier gas and laterally spaced away from the second terminal and operatively connected to the injector and the semiconductor region.

Abstract: A CMOS-based sensing device includes a substrate including an etched portion and a first region located on the substrate. The first region includes a membrane region formed over an area of the etched portion of the substrate, a flow sensor formed within the membrane region and a pressure sensor formed within the membrane region.

Abstract: There is disclosed herein a flow sensor comprising: a first substrate comprising an etched portion; a dielectric layer located on the first substrate, where the dielectric layer comprises at least one dielectric membrane located over the etched portion of the first substrate; a first heating element and a second heating element located on or within the dielectric membrane; and a controller coupled with the first heating element and the second heating element. The first heating element and the second heating element are arranged to intersect one another within or over an area of the dielectric membrane. The controller is configured to: take a measurement from the second heating element; determine a calibration parameter using the measurement from the second heating element; take a measurement from the first heating element; and determine a flow rate through the flow sensor using the determined calibration parameter and the measurement from the first heating element.

Abstract: We disclose herein a flow sensor comprising: a first substrate comprising an etched portion, a dielectric region located on a first side of the first substrate, wherein the dielectric region comprises at least one dielectric membrane located over the etched portion of the first substrate, a sensing element located on or within the dielectric membrane, and a second substrate adjoining a second side of the first substrate. The first side of the first substrate and the second side of the first substrate are opposite sides. The first substrate and the second substrate cooperate to form a sensing channel through the flow sensor.

Abstract: We disclose herein a flow and thermal conductivity sensor comprising a semiconductor substrate comprising an etched portion, a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises at least one dielectric membrane located over the etched portion of the semiconductor substrate and a heating element located within the dielectric membrane. The dielectric membrane comprises one or more discontinuities located between the heating element and an edge of the dielectric membrane.

Abstract: We disclose herein a flow sensor assembly comprising a first substrate, a flow sensor located over the first substrate, a lid located over the flow sensor, a flow inlet channel, and a flow outlet channel. A surface of the flow sensor and a surface of the lid cooperate to form a flow sensing channel between the flow inlet channel and the flow outlet channel, and a surface of the flow sensing channel is substantially flat throughout the length of the flow sensing channel.

Abstract: A heterojunction power device includes a substrate; a III-nitride semiconductor region over the substrate; a source operatively connected to the semiconductor region; a drain operatively connected to the semiconductor region; a gate between the source and drain and over the semiconductor region. The source is in contact with a first portion located between the source and gate and having a two dimensional carrier gas. The drain is in contact with a second portion located between the drain and gate and having a two dimensional carrier gas. At least one of the first and second portions has a trench having vertical sidewalls and formed within the semiconductor region; mesa regions extend away from each sidewall of the trench. The two dimensional carrier gas is located alongside the mesa regions and the trench. At least one of the source and drain is in contact with the respective two dimensional carrier gas.

Abstract: We disclose herein an infra-red (IR) device comprising a substrate comprising an etched cavity portion and a substrate portion; a dielectric layer disposed on the substrate. The dielectric layer comprises a dielectric membrane which is adjacent, or directly above, or below the etched cavity portion of the substrate. The device further comprises a reflective layer on or in or above or below the dielectric membrane to enhance emission or absorption of infrared light at one or more wavelengths.

Abstract: We disclose herein a depletion mode III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and a gate terminal formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension.

Abstract: We disclose a III-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first gate terminal formed over the first III-nitride semiconductor region between the first terminal and the second terminal.

Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on th

Abstract: We disclose a III-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first gate terminal formed over the first III-nitride semiconductor region between the first terminal and the second terminal.

Abstract: The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.

Abstract: A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.

Abstract: The invention relates to a deep depletion MIS transistor (100), comprising: a source region (S) and a drain region (D) made of doped semiconductor diamond of a first conductivity type; a channel region (C) made of doped semiconductor diamond of the first conductivity type, arranged between the source region and the drain region; a drift region (DR) made of doped semiconductor diamond of the first conductivity type, arranged between the channel region and the drain region; and a conductive gate (111) arranged on the channel region and separated from the channel region by a dielectric layer (113).

Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary gate terminal (15) and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device (205) and a low-voltage auxiliary GaN device (210) wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: A gas sensing device comprising a substrate comprising an etched cavity portion and a substrate portion; a dielectric layer disposed on the substrate. The dielectric layer comprises a dielectric membrane. The dielectric membrane is adjacent to the etched cavity portion of the substrate. The dielectric membrane comprises an etched recess portion, a heater located within the dielectric layer, and a material for sensing a gas. The material for sensing a gas is located within the etched recess portion of the dielectric membrane.

Abstract: A gas sensing device comprising a substrate comprising an etched cavity portion and a substrate portion, a dielectric layer disposed on the substrate, wherein the dielectric layer comprises a dielectric membrane, wherein the dielectric membrane is adjacent to the etched cavity portion of the substrate, a heater located within the dielectric layer; a material for sensing a gas; and one or more polysilicon electrodes coupled with the material for sensing a gas.

Abstract: We disclose an Infrared (IR) device comprising a first substrate comprising a first cavity; a dielectric layer disposed on the first substrate; a second substrate disposed on the dielectric layer and on the opposite side of the first substrate, the second substrate having a second cavity. The device further comprises an optically transmissive layer attached to one of the first and second substrates; a further layer provided to another of the first and second substrates so that the IR device is substantially closed. Holes are provided through the dielectric layer so that a pressure in the first cavity is substantially the same level as a pressure in the second cavity.