Patents by Inventor Frank Kuo
Frank Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140332939Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing dine.Type: ApplicationFiled: July 26, 2014Publication date: November 13, 2014Applicant: Siliconix Electronic Co., LTD.Inventors: Frank Kuo, Suresh Belani
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Publication number: 20140264804Abstract: In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. The gate and source are flip chip coupled to the lead frame. The stack die package can include a second die including a gate and a drain that are located on a first surface of the second die and a source that is located on a second surface of the second die that is opposite the first surface. The source of the second die is facing the drain of the first die.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: VISHAY-SILICONIXInventors: Kyle TERRILL, Frank KUO, Sen MAO
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Publication number: 20140273344Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: VISHAY-SILICONIXInventors: Kyle TERRILL, Frank KUO, Sen MAO
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Patent number: 8822273Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: GrantFiled: September 9, 2011Date of Patent: September 2, 2014Assignee: Vishay-SiliconixInventors: Frank Kuo, Suresh Belani
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Publication number: 20140208933Abstract: The present invention relates to a bicycle seat post structure, and more particularly, to a structure provided with a hydraulic actuator within which is configured with an upper oil compartment, an intermediate oil compartment, and a lower oil compartment; the three oil compartments intercommunicate. It is characterized in that the bicycle seat post structure provides an upper valve moving simultaneously with the pin and configured between the upper oil compartment and the intermediate oil compartment; the upper valve will be closed to disconnect the upper oil compartment from the intermediate oil compartment when the pin is in a state of locking. Thus, the valve will stop moving up because it is positioned above the upper and the intermediate oil compartments and consequently controlled by the oil within the compartments, so as to stop the seat sliding upward and further to be combined with the bicycle frame as a whole.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Inventor: Frank Kuo
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Publication number: 20140205372Abstract: The present invention provides a direction restricting device for the inner and outer tubes of a bicycle seat post, comprising at least one axial groove arranged on the wall of one of the tubes, and a direction restricting element fastened to the other tube at the position relative to the axial groove wall; said direction restricting element may be inserted into the axial groove and at least includes an elastic slider provided with an axial opening in the middle; the direction restricting element may be inserted into the axial groove so as to enable the axial outer walls of the direction restricting element to attach to the axial inner walls of the axial groove to eliminate the interspace between the slider and the axial groove to prevent from deflection and wobbling and to reinforce the steadiness of both tubes when the inner and outer tubes rotate relative to each other.Type: ApplicationFiled: June 10, 2013Publication date: July 24, 2014Inventor: Frank Kuo
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Patent number: 8586419Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.Type: GrantFiled: March 24, 2010Date of Patent: November 19, 2013Assignee: Vishay-SiliconixInventors: Serge Jaunay, Suresh Belani, Frank Kuo, Sen Mao, Peter Wang
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Patent number: 8471381Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: June 30, 2006Date of Patent: June 25, 2013Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Publication number: 20120112331Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.Type: ApplicationFiled: September 9, 2011Publication date: May 10, 2012Applicant: SILICONIX ELECTRONIC CO., LTD.Inventors: Frank Kuo, Suresh Belani
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Publication number: 20110175217Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.Type: ApplicationFiled: March 24, 2010Publication date: July 21, 2011Applicant: VISHAY-SILICONIXInventors: Serge Jaunay, Suresh Belani, Frank Kuo, Sen Mao, Peter Wang
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Publication number: 20100219519Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: May 13, 2010Publication date: September 2, 2010Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Publication number: 20090174055Abstract: An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (411) to die pads in cavities (41-45, 51-55) of a leadframe, the cavities arranged in a matrix of columns and rows; (b) electrically connecting the dice to a plurality of conducting portions (412-414) of the leadframe; and (c) longitudinally injecting molding material into the cavities along the columns via a plurality of longitudinal gates (46-49, 56-59) of the leadframe to package the dice in the cavities, the longitudinal gates situated between the cavities along the columns.Type: ApplicationFiled: March 10, 2009Publication date: July 9, 2009Applicant: VISHAY-SILICONIXInventor: Frank Kuo
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Patent number: 7501086Abstract: An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (411) to die pads in cavities (41-45, 51-55) of a leadframe, the cavities arranged in a matrix of columns and rows; (b) electrically connecting the dice to a plurality of conducting portions (412-414) of the leadframe; and (c) longitudinally injecting molding material into the cavities along the columns via a plurality of longitudinal gates (46-49, 56-59) of the leadframe to package the dice in the cavities, the longitudinal gates situated between the cavities along the columns.Type: GrantFiled: February 27, 2004Date of Patent: March 10, 2009Assignee: Vishay-SiliconixInventor: Frank Kuo
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Patent number: 7394150Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.Type: GrantFiled: November 23, 2004Date of Patent: July 1, 2008Assignee: Siliconix incorporatedInventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Robert Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen
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Patent number: 7238551Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.Type: GrantFiled: November 23, 2004Date of Patent: July 3, 2007Assignee: Siliconix incorporatedInventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Robert Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen
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Publication number: 20070063340Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: June 30, 2006Publication date: March 22, 2007Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Publication number: 20070063341Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: June 30, 2006Publication date: March 22, 2007Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Publication number: 20060108671Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.Type: ApplicationFiled: November 23, 2004Publication date: May 25, 2006Inventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen
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Publication number: 20060110856Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.Type: ApplicationFiled: November 23, 2004Publication date: May 25, 2006Inventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen
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Patent number: 6856006Abstract: An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (411) to die pads in cavities (41-45, 51-55) of a leadframe, the cavities arranged in a matrix of columns and rows; (b) electrically connecting the dice to a plurality of conducting portions (412-414) of the leadframe; and (c) longitudinally injecting molding material into the cavities along the columns via a plurality of longitudinal gates (46-49, 56-59) of the leadframe to package the dice in the cavities, the longitudinal gates situated between the cavities along the columns.Type: GrantFiled: March 28, 2002Date of Patent: February 15, 2005Assignee: Siliconix Taiwan LTDInventor: Frank Kuo