Abstract: Various methods and devices are provided for allowing multiple surgical instruments to be inserted into sealing elements of a single surgical access device. The sealing elements can be movable along predefined pathways within the device to allow surgical instruments inserted through the sealing elements to be moved laterally, rotationally, angularly, and vertically relative to a central longitudinal axis of the device for ease of manipulation within a patient's body while maintaining insufflation.

Abstract: A power amplifier with a quasi-static drain voltage adjustment is provided that has a transistor that is made from Gallium Nitride (GaN). In an exemplary aspect, the transistor is a field-effect transistor (FET) having a source, gate, and drain. The transistor is tested for process variations. Based on detected process variations, a microcontroller may raise a drain voltage to increase output power capability.

Abstract: A digital compensation system for a radio frequency (RF) power amplifier module is disclosed. The digital compensation system includes an RF power amplifier having a first input, a first output, and a first bias input, wherein the RF power amplifier is configured to receive an RF signal at the first input and generate an amplified version of the RF signal at the first output. The digital compensation system also includes compensation circuitry coupled between the first input and the first output and a bias output coupled to the RF power amplifier, wherein the compensation circuitry is configured, in response to the RF signal, to generate or adjust a bias signal at the first bias input to correct dynamic bias errors caused by amplification variations that have time constants.

Abstract: A method, apparatus, and device provide for the control of the power sourcing capability of a power source that supplies power to a device. A detection element of the device is operable to dynamically detect a power sourcing capability of the power source. A control element of the device is operable to monitor the detected power sourcing capability of the power source and to control the power source to effect a change in the power sourcing capability of the power source in response to a determination that the detected power sourcing capability of the power source is in violation of a threshold value.

Abstract: A method, system, and device provide asymmetric round-trip-time (RTT) ranging with multipath correction. A RTT ranging determination using the resulting composite received signal contains multipath error, and compensation or correction of this error in a manner compatible with low-power, low-complexity devices, such as tag devices, is provided.

Abstract: A method, apparatus, and device provide for the detection of insufficient supplied power supplied to a device. A current multiplier of the device, operable as a voltage regulator, is coupled to the power source, receives a clock signal, and generates a control signal. A digital counter, clocked by the clock signal and reset by the control signal, generates an overflow output in response to an overflow condition of the digital counter that indicates that the current sourcing capability of the power source has fallen below a current threshold of the device. A compensatory response by the device in response to the detection of insufficient supplied power may be provided as well.

Abstract: A method, apparatus, and device provide for the control of the power sourcing capability of a power source that supplies power to a device. A detection element of the device is operable to dynamically detect a power sourcing capability of the power source. A control element of the device is operable to monitor the detected power sourcing capability of the power source and to control the power source to effect a change in the power sourcing capability of the power source in response to a determination that the detected power sourcing capability of the power source is in violation of a threshold value.

Abstract: A method, apparatus, and device provide for the detection of insufficient supplied power supplied to a device. A current multiplier of the device, operable as a voltage regulator, is coupled to the power source, receives a clock signal, and generates a control signal. A digital counter, clocked by the clock signal and reset by the control signal, generates an overflow output in response to an overflow condition of the digital counter that indicates that the current sourcing capability of the power source has fallen below a current threshold of the device. A compensatory response by the device in response to the detection of insufficient supplied power may be provided as well.

Abstract: A method, system, and device provide asymmetric round-trip-time (RTT) ranging with multipath correction. A RTT ranging determination using the resulting composite received signal contains multipath error, and compensation or correction of this error in a manner compatible with low-power, low-complexity devices, such as tag devices, is provided.

Abstract: Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).

Abstract: A direct sequence spread spectrum (DSSS) receiver (100) consistent with certain embodiments has a frequency generator (112) that generates a local oscillator signal without use of a piezoelectric crystal. A frequency converter (108) receives the local oscillator signal and mixes the local oscillator signal with a received DSSS signal to produce a down-converted signal. The received DSSS signal is encoded using a first set of DSSS code. A differential chip detector (116) receives the down-converted signal and converts the down-converted signal to a differentially detected signal. A correlator (120) receives the differentially detected signal and correlates the detected signal with a set of DSSS codes that are time-shifted from the first set of DSSS codes. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A method (500) and system for compensation of frequency offset between a first transceiver (102) and a second transceiver (104) in wireless communication are disclosed. The compensation of the frequency offset between two or more transceivers (102, 104) is achieved using frequency synchronization bursts. These bursts contain information about the frequency offset. The frequency synchronization bursts are transmitted by the first transceiver at a range of frequencies above and below its carrier frequency (502). A second transceiver that receives at least one of these bursts (504) determines the frequency offset (504), and adjusts its frequency to match the frequency of the first transceiver (508). Thereafter, the second transceiver may enter a low power sleep mode (510) in order to reduce its power consumption. The second transceiver returns to active mode (512) just before the start of the transmission of the data packets (514).

Abstract: A method and location determination module is provided for determining a location of one of a plurality of units using neighbor lists. Each unit is communicatively coupled to at least some of the other plurality of units, where at least some of the plurality of units are reference units, whose locations are known. The units communicate with other nearby units within communication range, to establish neighbor lists. A unit to be located then identifies an aggregate value corresponding to the number of occurrences of the reference units in the neighbor list of the unit to be located and the neighbor lists of each of a group of associated units. The location of the unit to be located is then determined, based upon the known locations of the reference units and the number of identified occurrences of the reference units in the corresponding neighbor lists.

Abstract: A digital-to-phase or digital-to-time-shift converter (100) includes a delay line (106), a multiplexor (108) and synchronization circuit (110). In the converter (100) the clock edges of a reference signal are shifted in response to the value of a multi-bit digital word, IN (104). The synchronization circuit (110) gates the output of the multiplexor (108) such that a pulse appears at the synchronization circuit's (110) output port (114) only when the circuit is gated by a signal at input TRIG (112). The synchronization circuit (110) creates a time aperture for the multiplexor output.

Abstract: The present invention provides a multimode receiver design for mitigation of frequency offset by selective demodulation of an input modulated signal. The receiver (103) comprises a plurality of demodulators (207). Each of the plurality of demodulators (207) has the same functionality but different receiver sensitivity versus frequency-offset mitigation characteristics. Each of these demodulators incorporates a different demodulation technique. A suitable demodulator is selected to demodulate the received signal. The choice of a suitable demodulator is based on the value of the frequency offset (305, 307).

Abstract: A signaling system is provided in which a spread spectrum code is cyclically shifted by a cyclical shift dictated by a bit pattern of one or more bits. The cyclically shifted spread spectrum code is used to modulate a carrier frequency, and transmitted from a transmitter to a receiver. At the receiver the signal including the cyclically shifted spectrum code is demodulated to recover the cyclically shifted code. The cyclical shift is then determined and the bit pattern which is associated with the cyclical shift is output. The method can be used in direct sequence spread spectrum communication.

Abstract: A digital frequency synthesizer includes one or more reference clocks (104, 1316, 1502A, 1504A, 1506A) optionally coupled through one or more pulse width reducers (106) to one or more main delay lines (108, 702, 1502B, 1504B, 1506B) that include a plurality of output taps (108B-108I, 702B-702E). During at least certain periods of the reference clock (104) a plurality of the output taps are coupled to a common output (130, 1312, 1508), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates (114, 128, 720-724, 1420-1434) that are switched by gating pulses that are received from decoders (148, 150, 1418) via gating signal delay lines (134-146, 704-718, 1404-1416).

Abstract: A system for coarsely tuning at least one voltage controlled oscillator (VCO) (211) in a phase locked loop (PLL) synthesizer (200) that includes a phase-frequency detector (PFD) for determining a phase difference between a VCO frequency and a reference frequency and providing an error signal if the VCO frequency and reference frequency are at least 2&pgr; radians out of phase. A monitor (215) is then used for tracking the number of error signals produced by the PFD. The free running frequency of the VCO may be coarsely tuned in the event the monitor circuit reaches some predetermined level. The invention offers great advantage in enabling a PLL to be coarsely tuned to enable the PLL's VCO to remain with an operational range despite operational factors that effect circuit operation.

Abstract: A digital frequency synthesizer includes one or more reference clocks (104, 1316, 1502A, 1504A, 1506A) optionally coupled through one or more pulse width reducers (106) to one or more main delay lines (108, 702, 1502B, 1504B, 1506B) that include a plurality of output taps (108B-108I, 702B-702E). During at least certain periods of the reference clock (104) a plurality of the output taps are coupled to a common output (130, 1312, 1508), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates (114, 128, 720-724, 1420-1434) that are switched by gating pulses that are received from decoders (148, 150, 1418) via gating signal delay lines (134-146, 704-718, 1404-1416).

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.