Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

Abstract: A system and method for orthogonal modulation of signals in communication systems. In the transmitter, differentially coded symbols are used to select time-shifted code sequences. The timing, or code position, of a code sequence is determined at the receiver by comparison to the previous code from the same channel, thus eliminating the need for dual-channel transmission and eliminating error due to differences in path propagation time. A fixed preamble code is also used to synchronize the receiver.

Abstract: Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).

Abstract: A system and method for orthogonal modulation of signals in communication systems. In the transmitter, differentially coded symbols are used to select time-shifted code sequences. The timing, or code position, of a code sequence is determined at the receiver by comparison to the previous code from the same channel, thus eliminating the need for dual-channel transmission and eliminating error due to differences in path propagation time. A fixed preamble code is also used to synchronize the receiver.

Abstract: A signaling system is provided in which a spread spectrum code is cyclically shifted by a cyclical shift dictated by a bit pattern of one or more bits. The cyclically shifted spread spectrum code is used to modulate a carrier frequency, and transmitted from a transmitter to a receiver. At the receiver the signal including the cyclically shifted spectrum code is demodulated to recover the cyclically shifted code. The cyclical shift is then determined and the bit pattern which is associated with the cyclical shift is output. The method can be used in direct sequence spread spectrum communication.

Abstract: A signaling system is provided in which a spread spectrum code is cyclically shifted by a cyclical shift dictated by a bit pattern of one or more bits. The cyclically shifted spread spectrum code is used to modulate a carrier frequency, and transmitted from a transmitter to a receiver. At the receiver the signal including the cyclically shifted spectrum code is demodulated to recover the cyclically shifted code. The cyclical shift is then determined and the bit pattern which is associated with the cyclical shift is output. The method can be used in direct sequence spread spectrum communication.

Abstract: A frequency generation device (100) comprises a cascade of two phase-locked loops (104 and 108). The first PLL (104) is a frequency synthesizer while the second PLL, or offset loop (108), comprises a phase detector (208 or 306), loop filter (210 or 310), VCO (212 or 312) and a divider with near-unity modulus (204 or 308). In the case of a negative offset design, the near-unity divider (204) is placed in the offset loop feedback path. In a positive offset design, the near-unity divider (308) is placed in the path between the synthesizer VCO and the offset loop phase detector. Unlike existing art, there is no offset signal input to the second or offset loop (108).

Abstract: A phase detector circuit (100) operating at a high frequency includes a steering circuit (112) operating on frequency-divided versions of the phase detector signals. The phase detector (100) implements steering by adding dividers (108, 110) at both input ports to the steering circuit (112). This achieves the desired effect of reducing the operating frequency of the input signals to the steering circuit (112) to make operation possible at high frequencies of operation. The phase detector (100) also allows the steer circuit (112) to be turned off in steady state operation, this is accomplished by coupling only the steer outputs of the steering circuit (12) to the tuning line. The phase/frequency detect outputs are not coupled to the tuning line.

Abstract: A wideband level shift circuit (200) used with low voltage ECL or CML topologies. includes a sub-Vbe voltage reference (201) whose output voltage is offset some fraction of a diode voltage drop below a supply voltage, where the fraction is held at a constant value as the diode voltage varies with temperature. A comparator circuit (203) is attached to the reference voltage circuit (201) as well as to a current sourcing transistor and differential buffer circuit (205). The comparator circuit (203) maintains the DC potential at the output of a current sourcing transistor so that the common-mode DC level of the output signal from a differential buffer is shifted down by a fraction of a diode drop from the common-mode DC level of a wideband AC input signal. The shift circuit (200) offers the advantages of a fraction of a diode DC voltage drop with little loss of AC signal bandwidth for circuits operating from low supply voltages.

Abstract: A wideband level shift circuit (200) used with low voltage ECL or CML topologies includes a sub-Vbe voltage reference (201) whose output voltage is offset some fraction of a diode voltage drop below a supply voltage, where the fraction is held at a constant value as the diode voltage varies with temperature. A comparator circuit (203) is attached to the reference voltage circuit (201) as well as to a current sourcing transistor and differential buffer circuit (205). The comparator circuit (203) maintains the DC potential at the output of a current sourcing transistor so that the common-mode DC level of the output signal from a differential buffer is shifted down by a fraction of a diode drop from the common-mode DC level of a wideband AC input signal. The shift circuit (200) offers the advantages of a fraction of a diode DC voltage drop with little loss of AC signal bandwidth for circuits operating from low supply voltages.

Abstract: A temperature sensing apparatus (200), includes a temperature sensor (220), a current source (203), and a temperature independent voltage source (240, 250). The current source (203) provides a biasing current to the temperature sensor (220), and the voltage source (240, 250) is programmable to adjust the output of the temperature sensor (220). Preferably, the voltage source (240, 250) includes a variable current source (240) and a resistive element (250) with counterbalanced temperature coefficients, and the bias current source (203) is selected to have a counterbalancing temperature coefficient to that of the resistive element (250).

Abstract: A top coat nail polish composition, which is at least substantially free of ketones and aromatic solvents as well as formaldehyde containing resins and nitrocellulose, contains at least one cellulose ester, a mixture of aliphatic and cycloaliphatic solvents for the cellulose ester, a plasticizer for the cellulose ester, at least two UV blocking agents having different effective UV wavelength blockage ranges, a smoothing agent, an adhesion promoter, and an alkanol solvent for the smoothing agent and the adhesion promoter.

Abstract: A frequency synthesizer (100, 500) provides multiple selectable voltage controlled oscillator (VCO) frequency ranges. A VCO control circuit (114) controls the selectable VCO frequency ranges based on lock conditions of selected VCOs within a VCO array (112) or a single variable VCO circuit (502), to provide an extended tuning range to the frequency synthesizer (100, 500).

Abstract: A nail coating composition, which is substantially free to totally free of aromatic solvents, ketones, and formaldehyde containing resins, includes nitrocellulose, maleic modified rosin based resin, and polyester resin as the film forming polymers; sucrose acetate isobutyrate, butyl benzyl phthalate, and glyceryl tribenzoate as the plasticizers; at least one vitamin; at least one UV blocking agent; at least one protein; at least one moisturizer; at least one smoothing agent; at least one adhesion promoter; and a mixture of solvents, wherein all of the solvents in the composition are selected from the group consisting of alkanes having 4 to 10 carbon atoms, aliphatic esters having 3 to 10 carbon atoms, alkanols having 2 to 10 carbon atoms, cycloalkanes having 4 to 10 carbon atoms, cycloaliphatic esters having 4 to 10 carbon atoms, cycloalkanols having 4 to 10 carbon atoms, and mixtures of any two or more thereof.

Abstract: An automatic gain control circuit (100) provides precision gain control for amplified signals. An offset generator (130) generates an offset signal (132) from an output signal (108) of a variable gain amplifier, shifted according to a target signal level, and another offset signal (134) according to a base signal (106). A pulse train generator (140) compares the offset signals (108, 106) and provides a pulse train signal (142) having a particular energy content. A feedback signal (172) based on the particular energy content of the pulse train signal (142) is used to adjust the gain of the variable amplifier (110).

Abstract: A top coat nail polish composition, which is at least substantially free of aromatic solvents, contains at least one cellulose ester, a mixture of aliphatic and cycloaliphatic solvents for the cellulose ester, a plasticizer for the cellulose ester, at least two UV blocking agents having different effective UV wavelength blockage ranges, a smoothing agent, an adhesion promoter, and an alkanol solvent for the smoothing agent and the adhesion promoter.

Abstract: BiCMOS technology is used in the design of a VCO (200) to improve low DC operation. The VCO (200) includes two coupled oscillator circuits (201,219) tuned to different fixed frequencies such that the oscillator resonant frequencies define the tuning range of the VCO (200). The oscillator circuits (201, 219) are coupled such that the frequency of oscillation of the VCO (200) is adjustable via variable resistors (206, 214) by manipulating the bias currents to the two oscillator circuits (201,219). A biasing circuit (208) along with variable resistors (206 and 214) provide the DC bias to the oscillator circuits (201 and 219). The biasing circuit (208) maintains the sum of the biasing currents to the oscillator circuits constant. The oscillator circuits (201, and 219) are interconnected utilizing an RF coupling circuit (211). The VCO (200) is capable of operating at voltages as low as 1.8 volts DC.

Abstract: An electronic circuit (100) includes a load stage circuit (116) having at least one FET (118 and 120). The load stage circuit (116) includes an adjustment terminal responsive to an adjustment voltage for controlling the load resistance of the FET (118 and 120). The electronic circuit (100) also includes a bias current generator (124) for generating a bias current. A current steering circuit (122) controls the amount of bias current supplied to the load stage circuit (116). The electronic circuit (100) also includes a plurality of output terminals (112 and 114) for providing an output which is responsive to voltages applied at input terminals (104, 106 and 108) of the current steering circuit (122). Circuit (100) alllows for the adjustment of the bias current to the circuit in order to achieve optimum power dissipation over changing operating conditions.

Abstract: A top coat composition for application over a nail polish, consisting essentially of cellulose acetate butyrate resin, a mixture of solvents for dissolving the cellulose acetate butyrate resin to form a first solution, a plasticizer for the first solution, and a solvent for the plasticizer, providing a dry non-tacky, non-brittle solid coat and which is quick drying when applied over a nail polish while wet with improved hardness and gloss.

Abstract: Briefly, according to the invention, a multi-loop synthesizer (100) for producing an output signal (114) having minimum spurious components is described. The multi-loop synthesizer (100) includes a first synthesizer loop (116) which has a divider stage (108) and an oscillator stage (106) for providing an oscillator output signal (118). The multi-loop synthesizer (100) also includes at least one additional synthesizer loop (121) which also has an output for providing a loop output signal (120). The multi-loop synthesizer (100) further includes an image balanced mixer (110) coupled to the divider stage (108) of the first synthesizer loop for mixing the oscillator output signal (118) of the first synthesizer loop (116) with the loop output (120) of the at least one additional synthesizer loop (121).