Abstract: A backside illuminated image sensor comprises a sensor layer having a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. A color filter array is formed on a backside surface of the oxide layer, and a transparent cover is attached to the backside surface of the oxide layer overlying the color filter array. Redistribution metal conductors are in electrical contact with respective bond pad conductors through respective openings in the dielectric layer. A redistribution passivation layer is formed over the redistribution metal conductors, and contact metallizations are in electrical contact with respective ones of the respective redistribution metal conductors through respective openings in the redistribution passivation layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Abstract: A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. The sensor layer further comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements. The backside trenches have corresponding backside field isolation implant regions formed in the sensor layer, and the resulting structure provides reductions in carrier recombination and crosstalk between adjacent photosensitive elements. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Abstract: A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Abstract: A method and structure for providing a high energy implant in only the red pixel location of a CMOS image sensor. The implant increases the photon collection depth for the red pixels, which in turn increases the quantum efficiency for the red pixels. In one embodiment, a CMOS image sensor is formed on an p-type substrate and the high energy implant is a p-type implant that creates a p-type ground contact under the red pixel, thus reducing dark non-uniformity effects. In another embodiment, a CMOS image sensor is formed on an n-type substrate and a high energy p-type implant creates a p-type region under only the red pixel to increase photon collection depth, which in turn increases the quantum efficiency for the red pixels.

Abstract: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate.

Abstract: In integrated circuit that yields the advantages of contemporary processing technologies and yet is irreparably damaged by ionizing radiation. An integrated circuit is designed and fabricated with contemporary processing technologies in well-known fashion, except that certain devices, called “safeguard” devices, are added to the integrated circuit. The safeguard devices are fabricated so that they, and not the other devices on the integrated circuit, are susceptible to ionizing radiation. Furthermore, the safeguard devices are coupled to the utile devices on the integrated circuit in such a manner than when the integrated circuit is bombarded with ionizing radiation the safeguard devices short and destroy the functionality of the utile devices, and, therefore, the functionality of the integrated circuit.

Abstract: A method and an apparatus for manufacturing, via a single fabrication line, circuits that are radiation tolerant and also circuits that are radiation intolerant. When production calls for radiation-tolerant circuits, low-pressure chemical vapor deposition is advantageously used to deposit an electrically-insulating material, such as silicon dioxide, in trenches to provide electrical isolation between adjacent semiconductor devices. When production requires radiation-intolerant circuits, as may be required for export, then the trenches are filled via a procedure that deposits an electrically-insulating material that, on exposure to ionizing radiation, generates a suitably large amount of “positive charge traps.” One procedure suitable for creating such positive charge traps is high-density plasma chemical vapor deposition (HDPCVD).

Abstract: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: A radiation-susceptible integrated circuit comprises radiation sensor, a differential amplifier and circuit disabler. The radiation sensor includes two devices that have a different tolerance to ionizing radiation. When exposed to a total dose of ionizing radiation that exceeds the radiation tolerance of one of the devices but not the other, only the more radiation-susceptible device will exhibit an increase in leakage current. The differential amplifier is operable to generate an output signal having a value that is indicative of a difference or offset that exists between the output of the two devices. The output signal from the differential amplifier is received by the circuit disabler, which is activated, or not, as a function of the value of the output signal.

Abstract: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate.

Abstract: Neutral conductivity ions, preferably germanium, are implanted through the oxide of a metal oxide semiconductor after isolation formation to provide a nearly constant threshold voltage for transistor operation independent of transistor channel width as device geometries are scaled down in size. The present invention sets forth a method for fabricating a metal oxide semiconductor (MOS) structure that controls threshold voltage Vt in the structure, the method including generating an isolation region of the semiconductor structure on a major surface of a silicon substrate, growing a thin oxide on the major surface of the semiconductor structure, implanting a large diameter neutral conductivity type ion into the major surface of the semiconductor structure through the thin oxide, annealing the semiconductor structure having the neutral conductivity ion implanted therein, and processing the semiconductor structure to create MOS devices having a near constant threshold voltage over a range of device channel widths.

Abstract: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate.

Abstract: A method and an apparatus for manufacturing, via a single fabrication line, circuits that are radiation tolerant and also circuits that are radiation intolerant. When production calls for radiation-tolerant circuits, low-pressure chemical vapor deposition is advantageously used to deposit an electrically-insulating material, such as silicon dioxide, in trenches to provide electrical isolation between adjacent semiconductor devices. When production requires radiation-intolerant circuits, as may be required for export, then the trenches are filled via a procedure that deposits an electrically-insulating material that, on exposure to ionizing radiation, generates a suitably large amount of “positive charge traps.” One procedure suitable for creating such positive charge traps is high-density plasma chemical vapor deposition (HDPCVD).

Abstract: Semiconductor devices and integrated circuits that benefit from the advantages of contemporary processing technologies yet are irreparably damaged by ionizing radiation, and methods for making the same. Transistors that are particularly intolerant to ionizing radiation have a gate insulator that includes a portion of a screen layer that is used in conjunction with N- and P-well implantation. After the implantation step, the screen layer exhibits significantly degraded tolerance to ionizing radiation, so that a gate insulator incorporating a portion of such a screen layer will likewise be radiation intolerant. By selectively removing portions of the screen layer, a method is provided for co-locating radiation-tolerant and radiation-intolerant transistors on a substrate. A radiation intolerant integrated circuit is formed by adding “safeguard devices” to an integrated circuit.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: Neutral conductivity ions, preferably germanium, are implanted through the oxide of a metal oxide semiconductor after isolation formation to provide a nearly constant threshold voltage for transistor operation independent of transistor channel width as device geometries are scaled down in size. The present invention sets forth a method for fabricating a metal oxide semiconductor (MOS) structure that controls threshold voltage Vt in the structure, the method including generating an isolation region of the semiconductor structure on a major surface of a silicon substrate, growing a thin oxide on the major surface of the semiconductor structure, implanting a large diameter neutral conductivity type ion into the major surface of the semiconductor structure through the thin oxide, annealing the semiconductor structure having the neutral conductivity ion implanted therein, and processing the semiconductor structure to create MOS devices having a near constant threshold voltage over a range of device channel widths.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: An ESD protection arrangement for a silicon-on-insulator device has an N-well type implant in the silicon substrate of the device, a p.sup.+ implant forming a juncture with the N-well type implant, and an n.sup.+ implant defining a juncture with the N-well type implant, in order to protect against negative transients and positive transients. At the p-channel threshold adjust, both the p-channel of the device and the N-well are implanted. Implanting the N-well to a depth of about 0.15 to about 0.30 .mu.m provides suitable characteristics for both the N-well and the p-channel.

Abstract: SOI (silicon-on-insulator) technology has been touted as a promising approach for fabricating advanced integrated circuits because of its advantage over bulk silicon circuits such as faster speed and improved radiation tolerance. One drawback to SOI is that parasitic bipolar induced latch-up/breakdown voltage levels severely limits the maximum supply voltage at which SOI circuits and devices can operate. When the parasitic device turns on, the SOI transistor cannot be switched off by changing the gate bias. What is described is a method whereby the operating voltage in which this effect occurs is significantly increased thus allowing circuit operation at reasonable power supply voltages. The method is to implant an electrically neutral in silicon impurity atom such as krypton, xenon or germanium into the device to form ion scattering centers. The size of the impurity atom must be much larger than the size of the silicon atom. The size difference generating a scattering center.