Patents by Inventor Fumiki Aiso
Fumiki Aiso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096669Abstract: A substrate processing apparatus according to an embodiment includes a boat capable of accommodating a plurality of substrates taken out from a storage container, a reactor capable of housing the boat and processing the plurality of substrates, and first and second arms that transfer the plurality of substrates. The boat accommodates the substrates in a first direction intersecting surfaces of the substrates. The first arm holds both ends of one substrate in a second direction intersecting the first direction, and is capable of transferring the one substrate between the storage container and the second arm. The second arm has a first holder that can support two substrates in a third direction intersecting the first and second directions, and is capable of transferring the two substrates between the first arm and the boat.Type: ApplicationFiled: September 5, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventor: Fumiki AISO
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Publication number: 20230091037Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a chamber on which a substrate is placed, a first gas flow path configured to supply a first processing gas into the chamber, a second gas flow path configured to supply a second processing gas into the chamber, a first replacement gas flow path configured to supply a first replacement gas into the chamber, a replacement gas heating unit configured to heat the first replacement gas, a second replacement gas flow path configured to supply a second replacement gas into the chamber, and a replacement gas cooling unit configured to cool the second replacement gas.Type: ApplicationFiled: March 14, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventor: Fumiki AISO
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Publication number: 20220301870Abstract: According to an embodiment, a semiconductor manufacturing method includes forming a first seed layer on an underlying layer with a first gas that is an aminosilane gas. The method further includes forming a first amorphous silicon layer on the first seed layer with a second gas that is a silane gas not containing an amino group. The method further includes forming a second seed layer containing impurities on the first amorphous silicon layer with a third gas that is an aminosilane gas. The method further includes forming a second amorphous silicon layer on the second seed layer with a fourth gas that is a silane gas not containing an amino group.Type: ApplicationFiled: September 14, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Atsushi FUKUMOTO, Fumiki AISO
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Publication number: 20220270885Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a substrate processor configured to process a substrate with a gas of a first substance and a gas of a second substance, and discharge a first gas including the first substance and/or the second substance. The apparatus further includes a disposer configured to discard the first gas discharged from the substrate processor. The apparatus further includes a recoverer configured to generate a second gas including the second substance by using the first substance in the first gas discharged from the substrate processor, and supply the second gas to the substrate processor.Type: ApplicationFiled: September 14, 2021Publication date: August 25, 2022Applicant: Kioxia CorporationInventors: Motoki FUJII, Hiroshi KUBOTA, Fumiki AISO
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Publication number: 20220077170Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.Type: ApplicationFiled: November 12, 2021Publication date: March 10, 2022Inventors: Yoshiaki FUKUZUMI, Keisuke SUDA, Fumiki AISO, Atsushi FUKUMOTO
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Publication number: 20210010134Abstract: According to an embodiment, a semiconductor manufacturing apparatus includes a chamber, a process gas nozzle, an inert gas nozzle and a hydrogen radical nozzle. The chamber houses at least one substrate. The process gas nozzle is to release process gas toward the substrate in the chamber. The inert gas nozzle is to release inert gas toward the substrate in the chamber. The hydrogen radical nozzle is disposed in the chamber and is to generate hydrogen radicals by heating raw material gas including hydrogen and to release the generated hydrogen radicals toward the substrate during the release of the inert gas. A metal wire is in the hydrogen radical nozzle, and the metal wire includes a metal catalyst for exciting the generation of the hydrogen radicals.Type: ApplicationFiled: September 22, 2020Publication date: January 14, 2021Applicant: Toshiba Memory CorporationInventors: Fumiki Aiso, Kensei Takahashi, Tomohisa Iino
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Patent number: 10854488Abstract: A wafer conveying apparatus conveying a wafer onto a supporting table in manufacturing a semiconductor. A first arm retains the wafer to move to an upper region of the supporting table, and is retracted from the upper region of the supporting table after the wafer is elevated. A second arm contacts the wafer by an opening provided in the supporting table to elevate the wafer, and lowers the wafer to place the wafer on the supporting table.Type: GrantFiled: July 26, 2019Date of Patent: December 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Fumiki Aiso, Ryota Fujitsuka, Kensei Takahashi, Takayuki Matsui, Tomohisa Iino
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Patent number: 10669621Abstract: According to the embodiment, a vaporization system includes a vaporizer, a body, a sensor, a moving mechanism, and a supplier. The vaporizer includes a plurality of containers which can store powdered solid materials. The body in a vacuum state can house the vaporizer. The sensor detects a residue of the solid materials stored in a plurality of the containers respectively. The moving mechanism, on the basis of a detection result of the sensor, moves the plurality of the containers respectively between a first position located inside the vaporizer, and a second position located outside of the vaporizer. A supplier supplies the solid material to the container located in the second position among the plurality of the containers.Type: GrantFiled: February 13, 2017Date of Patent: June 2, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Fumiki Aiso, Hajime Nagano, Kensei Takahashi, Tomohisa Iino
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Publication number: 20190348314Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a container to contain wafers, and supporting tables provided in the container so as to be stacked on one another, and each including a supporting face that comes into contact with a wafer to support the wafer. The apparatus further includes supporting columns to join the supporting tables together and provided at positions where the supporting columns are contained inside outer circumferences of the supporting tables. The apparatus further includes a gas feeder to feed a gas to the wafers on the supporting tables, and a gas discharger to discharge the gas fed to the wafers on the supporting tables. Each of the supporting tables includes a first upper face as the supporting face, and a second upper face provided so as to surround the first upper face at a level higher than a level of the first upper face.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Fumiki AISO, Ryota Fujitsuka, Kensei Takahashi, Takayuki Matsui, Tomohisa Iino
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Publication number: 20190326310Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.Type: ApplicationFiled: March 4, 2019Publication date: October 24, 2019Inventors: Yoshiaki FUKUZUMI, Keisuke SUDA, Fumiki AISO, Atsushi FUKUMOTO
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Patent number: 10403531Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a container to contain wafers, and supporting tables provided in the container so as to be stacked on one another, and each including a supporting face that comes into contact with a wafer to support the wafer. The apparatus further includes supporting columns to join the supporting tables together and provided at positions where the supporting columns are contained inside outer circumferences of the supporting tables. The apparatus further includes a gas feeder to feed a gas to the wafers on the supporting tables, and a gas discharger to discharge the gas fed to the wafers on the supporting tables. Each of the supporting tables includes a first upper face as the supporting face, and a second upper face provided so as to surround the first upper face at a level higher than a level of the first upper face.Type: GrantFiled: March 8, 2018Date of Patent: September 3, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Fumiki Aiso, Ryota Fujitsuka, Kensei Takahashi, Takayuki Matsui, Tomohisa Iino
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Patent number: 10283517Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.Type: GrantFiled: September 13, 2017Date of Patent: May 7, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takuo Ohashi, Fumiki Aiso
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Publication number: 20190071771Abstract: According to an embodiment, a semiconductor manufacturing apparatus includes a chamber, a process gas nozzle, an inert gas nozzle and a hydrogen radical nozzle. The chamber houses at least one substrate. The process gas nozzle is to release process gas toward the substrate in the chamber. The inert gas nozzle is to release inert gas toward the substrate in the chamber. The hydrogen radical nozzle is disposed in the chamber and is to generate hydrogen radicals by heating raw material gas including hydrogen and to release the generated hydrogen radicals toward the substrate during the release of the inert gas. A metal wire is in the hydrogen radical nozzle, and the metal wire includes a metal catalyst for exciting the generation of the hydrogen radicals.Type: ApplicationFiled: March 13, 2018Publication date: March 7, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Fumiki AISO, Kensei TAKAHASHI, Tomohisa IINO
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Publication number: 20190067066Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a container to contain wafers, and supporting tables provided in the container so as to be stacked on one another, and each including a supporting face that comes into contact with a wafer to support the wafer. The apparatus further includes supporting columns to join the supporting tables together and provided at positions where the supporting columns are contained inside outer circumferences of the supporting tables. The apparatus further includes a gas feeder to feed a gas to the wafers on the supporting tables, and a gas discharger to discharge the gas fed to the wafers on the supporting tables. Each of the supporting tables includes a first upper face as the supporting face, and a second upper face provided so as to surround the first upper face at a level higher than a level of the first upper face.Type: ApplicationFiled: March 8, 2018Publication date: February 28, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Fumiki AISO, Ryota FUJITSUKA, Kensei TAKAHASHI, Takayuki MATSUI, Tomohisa IINO
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Patent number: 10186521Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending through the stacked body in a stacking direction of the stacked body, and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor body includes a first semiconductor film, and a second semiconductor film provided between the first semiconductor film and the charge storage portion. An average grain size of a crystal of the second semiconductor film is larger than an average grain size of a crystal of the first semiconductor film.Type: GrantFiled: March 15, 2017Date of Patent: January 22, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Fukumoto, Fumiki Aiso, Hajime Nagano, Takuo Ohashi
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Publication number: 20180277400Abstract: According to an embodiment, a semiconductor manufacturing apparatus includes a process chamber, a load lock chamber, a gas purge mechanism and a movement mechanism. The process chamber treats a substrate using process gas in a vacuum state. The load lock chamber temporarily houses the substrate while holding the vacuum state. The gas purge mechanism is in the process chamber or the load lock chamber. The movement mechanism retains the substrate below the gas purge mechanism. The gas purge mechanism includes a plurality of gas feed ports opposing to the movement mechanism and to eject inactive gas at a first pressure higher than an atmospheric pressure, and a plurality of gas discharge ports provided alternately along with the plurality of gas feed ports along a movement direction of the movement mechanism and to discharge the process gas and the inactive gas at a second pressure lower than the atmospheric pressure.Type: ApplicationFiled: September 8, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventor: Fumiki AISO
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Publication number: 20180083028Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending through the stacked body in a stacking direction of the stacked body, and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor body includes a first semiconductor film, and a second semiconductor film provided between the first semiconductor film and the charge storage portion. An average grain size of a crystal of the second semiconductor film is larger than an average grain size of a crystal of the first semiconductor film.Type: ApplicationFiled: March 15, 2017Publication date: March 22, 2018Applicant: Toshiba Memory CorporationInventors: Atsushi FUKUMOTO, Fumiki AISO, Hajime NAGANO, Takuo OHASHI
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Patent number: 9920427Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a reaction chamber in which a semiconductor substrate is capable of being accommodated when a deposited film is to be formed on a surface of the semiconductor substrate. A first supplier supplies a source gas to a first area in the reaction chamber. A second supplier supplies an oxidation gas to a second area in the reaction chamber. A third supplier supplies a hydrogen gas to a third area between the first area and the second area in the reaction chamber. A stage moves the semiconductor substrate to any one of the first to third areas.Type: GrantFiled: June 26, 2015Date of Patent: March 20, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Motoki Fujii, Fumiki Aiso, Hajime Nagano, Ryota Fujitsuka
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Publication number: 20180057926Abstract: According to the embodiment, a vaporization system includes a vaporizer, a body, a sensor, a moving mechanism, and a supplier. The vaporizer includes a plurality of containers which can store powdered solid materials. The body in a vacuum state can house the vaporizer. The sensor detects a residue of the solid materials stored in a plurality of the containers respectively. The moving mechanism, on the basis of a detection result of the sensor, moves the plurality of the containers respectively between a first position located inside the vaporizer, and a second position located outside of the vaporizer. A supplier supplies the solid material to the container located in the second position among the plurality of the containers.Type: ApplicationFiled: February 13, 2017Publication date: March 1, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Fumiki AISO, Hajime NAGANO, Kensei TAKAHASHI, Tomohisa llNO
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Publication number: 20180006053Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.Type: ApplicationFiled: September 13, 2017Publication date: January 4, 2018Applicant: Toshiba Memory CorporationInventors: Takuo OHASHI, Fumiki AISO