Patents by Inventor Fumiki Aiso
Fumiki Aiso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9793290Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.Type: GrantFiled: March 16, 2016Date of Patent: October 17, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takuo Ohashi, Fumiki Aiso
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Patent number: 9754954Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: GrantFiled: July 5, 2016Date of Patent: September 5, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
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Patent number: 9735171Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction crossing the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A gap is provided between the semiconductor layer and a lower end portion of the charge accumulation layer.Type: GrantFiled: March 16, 2016Date of Patent: August 15, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Junya Fujita, Fumiki Aiso
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Publication number: 20170229473Abstract: According to an embodiment, a semiconductor memory device includes first and second stacked bodies, first and second memory parts, and an insulating part. The first stacked body includes first conductive layers and first insulating layers alternately arranged in a first direction. The second stacked body includes second conductive layers and second insulating layers alternately arranged in the first direction. The first and second memory parts extend through the first and second stacked body in the first direction, respectively. The insulating part is provided between the first and second stacked bodies. The insulating part includes a first oxygen-containing film including silicon and oxygen, and a nitrogen-containing film including silicon and nitrogen. The first oxygen-containing film is provided between at least one of first conductive layers and the nitrogen-containing film. The first oxygen-containing film has a hole.Type: ApplicationFiled: July 8, 2016Publication date: August 10, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi FUKUMOTO, Fumiki AISO, Hajime NAGANO
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Patent number: 9728552Abstract: According to an embodiment, a semiconductor memory device includes first and second stacked bodies, first and second memory parts, and an insulating part. The first stacked body includes first conductive layers and first insulating layers alternately arranged in a first direction. The second stacked body includes second conductive layers and second insulating layers alternately arranged in the first direction. The first and second memory parts extend through the first and second stacked body in the first direction, respectively. The insulating part is provided between the first and second stacked bodies. The insulating part includes a first oxygen-containing film including silicon and oxygen, and a nitrogen-containing film including silicon and nitrogen. The first oxygen-containing film is provided between at least one of first conductive layers and the nitrogen-containing film. The first oxygen-containing film has a hole.Type: GrantFiled: July 8, 2016Date of Patent: August 8, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Fukumoto, Fumiki Aiso, Hajime Nagano
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Patent number: 9695512Abstract: In one embodiment, a semiconductor manufacturing system includes a film forming apparatus configured to form a film on a surface of a wafer. The system further includes a gas supply module configured to supply at least a type of source gas for the film into the film forming apparatus. The system further includes a measurement module configured to measure a discharge amount of an exhaust gas from the film forming apparatus. The system further includes a controller configured to calculate a value corresponding to a surface area of the wafer based on the discharge amount of the exhaust gas from the film forming apparatus, and to control a supply amount of the source gas to the film forming apparatus based on the value corresponding to the surface area of the wafer.Type: GrantFiled: February 5, 2015Date of Patent: July 4, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Matsuo, Fumiki Aiso
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Patent number: 9566620Abstract: An LPCVD apparatus is provided with a processing chamber and a reaction cooling apparatus. The reaction cooling apparatus is placed outside the processing chamber and is configured to generate hydrogen fluoride gas by reaction of hydrogen gas and fluorine gas and to cool the hydrogen fluoride gas. The hydrogen fluoride gas cooled by the reaction cooling apparatus is supplied into the processing chamber as a cleaning gas.Type: GrantFiled: August 6, 2013Date of Patent: February 14, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kenichiro Toratani, Fumiki Aiso, Takashi Nakao, Kazuhei Yoshinaga
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Publication number: 20170018568Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction crossing the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A gap is provided between the semiconductor layer and a lower end portion of the charge accumulation layer.Type: ApplicationFiled: March 16, 2016Publication date: January 19, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Junya FUJITA, Fumiki AISO
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Publication number: 20170018569Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.Type: ApplicationFiled: March 16, 2016Publication date: January 19, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takuo OHASHI, Fumiki AISO
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Publication number: 20160315092Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: ApplicationFiled: July 5, 2016Publication date: October 27, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Fumiki AISO, Takuo OHASHI, Tatsuya OKAMOTO
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Patent number: 9478416Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a belt supporting module including a first portion that is provided around a first axis, a second portion that is provided around a second axis different from the first axis, a third portion connecting the first and second portions, and a fourth portion connecting the first and second portions and positioned below the third portion. The apparatus further includes a belt provided on the belt supporting module, and configured to rotate around the first axis in a first direction and rotate around the second axis in a second direction reverse to the first direction. The apparatus further includes a wafer supporting module provided on the belt and configured to support a wafer. The apparatus further includes raw material feeding heads provided above the belt and configured to feed a raw material of a film to be formed on the wafer.Type: GrantFiled: February 9, 2016Date of Patent: October 25, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi Fukumoto, Fumiki Aiso, Takeshi Shundo, Hajime Nagano
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Publication number: 20160222514Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a reaction chamber in which a semiconductor substrate is capable of being accommodated when a deposited film is to be formed on a surface of the semiconductor substrate. A first supplier supplies a source gas to a first area in the reaction chamber. A second supplier supplies an oxidation gas to a second area in the reaction chamber. A third supplier supplies a hydrogen gas to a third area between the first area and the second area in the reaction chamber. A stage moves the semiconductor substrate to any one of the first to third areas.Type: ApplicationFiled: June 26, 2015Publication date: August 4, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Motoki FUJII, Fumiki AISO, Hajime NAGANO, Ryota FUJITSUKA
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Patent number: 9406691Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: GrantFiled: September 24, 2015Date of Patent: August 2, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
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Publication number: 20160208382Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a reaction chamber that is capable of housing a semiconductor substrate and is capable of forming a deposited film on a surface of the semiconductor substrate. A first container stores a source of the deposited film. A second container stores a source gas generated in the first container, and supplies the source gas to the reaction chamber. A first pipe connects the first container and the second container. A second pipe supplies an inert gas to the second container.Type: ApplicationFiled: July 29, 2015Publication date: July 21, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kensei Takahashi, Kazuhiro Matsuo, Fumiki Aiso
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Publication number: 20160060762Abstract: In one embodiment, a semiconductor manufacturing system includes a film forming apparatus configured to form a film on a surface of a wafer. The system further includes a gas supply module configured to supply at least a type of source gas for the film into the film forming apparatus. The system further includes a measurement module configured to measure a discharge amount of an exhaust gas from the film forming apparatus. The system further includes a controller configured to calculate a value corresponding to a surface area of the wafer based on the discharge amount of the exhaust gas from the film forming apparatus, and to control a supply amount of the source gas to the film forming apparatus based on the value corresponding to the surface area of the wafer.Type: ApplicationFiled: February 5, 2015Publication date: March 3, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro MATSUO, Fumiki Aiso
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Patent number: 9263319Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode.Type: GrantFiled: June 9, 2014Date of Patent: February 16, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Fujitsuka, Fumiki Aiso, Motoki Fujii, Hiroshi Itokawa
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Publication number: 20160013201Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: ApplicationFiled: September 24, 2015Publication date: January 14, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Fumiki AISO, Takuo OHASHI, Tatsuya OKAMOTO
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Patent number: 9224874Abstract: A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A tunnel insulating film is provided on the semiconductor substrate. A charge accumulation layer is provided on the tunnel insulating film. An intermediate dielectric film is provided on the charge accumulation layer. A control gate electrode is formed on the intermediate dielectric film. The intermediate dielectric film includes a laminated film of silicon oxide films of multiple layers and silicon nitride films of at least one layer, and a silicon oxynitride film provided between adjacent ones of the silicon oxide films and the silicon nitride films.Type: GrantFiled: March 7, 2014Date of Patent: December 29, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Matsuo, Masayuki Tanaka, Masao Shingu, Kensei Takahashi, Fumiki Aiso
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Patent number: 9166032Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: GrantFiled: September 11, 2014Date of Patent: October 20, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
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Patent number: 9142561Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of first semiconductor regions; a plurality of control gate electrodes; a charge storage layer; a first insulating film provided between the charge storage layer and first semiconductor regions; a second insulating film provided between the charge storage layer and control gate electrodes; and an element isolation region provided between the plurality of first semiconductor regions, and the element isolation region being in contact with the first insulating film and a first portion of the charge storage layer on the first insulating film side. Each of the plurality of control gate electrodes is in contact with a second portion other than the first portion of the charge storage layer. The charge storage layer includes a silicon-containing layer in contact with the first insulating film and a silicide-containing layer provided on the silicon-containing layer.Type: GrantFiled: September 5, 2013Date of Patent: September 22, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Fumiki Aiso