Patents by Inventor Fumiki Aiso

Fumiki Aiso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7906809
    Abstract: A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is substantially in agreement with a predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate, and at least one of orthographic projection images of cross-sections taken along planes parallel with the semiconductor silicon substrate of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is larger than the predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: March 15, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Fumiki Aiso
  • Patent number: 7863166
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Patent number: 7858508
    Abstract: In a method of manufacturing a semiconductor device, a trench is formed to have an upper quadrangular section and a lower circular section which is formed through a hydrogen annealing process, to extend in a depth direction of a semiconductor substrate. An insulating film is formed on a surface of the trench and a surface of the semiconductor substrate. A conductive film is formed to fill the trench whose surface is covered with the an insulating film. Source/drain regions are formed on both sides of the trench.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: December 28, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Yasuhiko Ueda, Fumiki Aiso, Yuki Koga
  • Patent number: 7842564
    Abstract: In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: November 30, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Hirokazu Ishida, Yoshio Ozawa, Takashi Suzuki, Fumiki Aiso, Makoto Mizukami
  • Publication number: 20100117135
    Abstract: A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a secon
    Type: Application
    Filed: September 22, 2009
    Publication date: May 13, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Makoto MIZUKAMI, Kiyohito Nishihara, Masaki Kondo, Takashi Izumida, Hirokazu Ishida, Atsushi Fukumoto, Fumiki Aiso, Daigo Ichinose, Tadashi Iguchi
  • Publication number: 20100112791
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Application
    Filed: December 23, 2009
    Publication date: May 6, 2010
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Publication number: 20100078622
    Abstract: A nonvolatile memory device includes: a substrate; a stacked structure member including a plurality of dielectric films and a plurality of electrode films alternately stacked on the substrate and including a through-hole penetrating through the plurality of the dielectric films and the plurality of the electrode films in a stacking direction of the plurality of the dielectric films and the plurality of the electrode films; a semiconductor pillar provided in the through-hole; and a charge storage layer provided between the semiconductor pillar and each of the plurality of the electrode films. At least one of the dielectric films includes a film generating one of a compressive stress and a tensile stress, and at least one of the electrode films includes a film generating the other of the compressive stress and the tensile stress.
    Type: Application
    Filed: September 4, 2009
    Publication date: April 1, 2010
    Inventors: Yasuhito Yoshimizu, Fumiki Aiso, Atsushi Fukumoto, Takashi Nakao
  • Publication number: 20100078045
    Abstract: An LPCVD apparatus is provided with a processing chamber and a reaction cooling apparatus. The reaction cooling apparatus is placed outside the processing chamber and is configured to generate hydrogen fluoride gas by reaction of hydrogen gas and fluorine gas and to cool the hydrogen fluoride gas. The hydrogen fluoride gas cooled by the reaction cooling apparatus is supplied into the processing chamber as a cleaning gas.
    Type: Application
    Filed: September 10, 2009
    Publication date: April 1, 2010
    Inventors: Kenichiro TORATANI, Fumiki Aiso, Takashi Nakao, Kazuhei Yoshinaga
  • Patent number: 7651930
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: January 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Publication number: 20090294828
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.
    Type: Application
    Filed: March 17, 2009
    Publication date: December 3, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshio Ozawa, Fumiki Aiso
  • Publication number: 20090130823
    Abstract: A method of forming a semiconductor device is provided, which may include, but is not limited to, the following processes. Grooves may be formed in an insulating region and in a semiconductor region, while forming burrs near the boundary between the insulating region and the semiconductor region. Protection films may be selectively formed on inside walls of the grooves except on bottom walls of the grooves. A selective thermal process may be carried out in the presence of the protection films, thereby removing the burrs.
    Type: Application
    Filed: November 14, 2008
    Publication date: May 21, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Kyoko MIYATA, Fumiki AISO
  • Publication number: 20090072324
    Abstract: A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is substantially in agreement with a predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate, and at least one of orthographic projection images of cross-sections taken along planes parallel with the semiconductor silicon substrate of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is larger than the predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate.
    Type: Application
    Filed: November 17, 2008
    Publication date: March 19, 2009
    Applicant: ELPIDA MEMORY INC.
    Inventor: Fumiki AISO
  • Patent number: 7482235
    Abstract: A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is substantially in agreement with a predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate, and at least one of orthographic projection images of cross-sections taken along planes parallel with the semiconductor silicon substrate of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is larger than the predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: January 27, 2009
    Assignee: Elpida Memory Inc.
    Inventor: Fumiki Aiso
  • Publication number: 20090014828
    Abstract: In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 15, 2009
    Inventors: Ichiro MIZUSHIMA, Hirokazu Ishida, Yoshio Ozawa, Takashi Suzuki, Fumiki Aiso, Makoto Mizukami
  • Publication number: 20090004833
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Patent number: 7470961
    Abstract: A semiconductor device provided with a semiconductor silicon substrate and gate wiring provided on the semiconductor silicon substrate via a gate oxide film, where the gate wiring has a gate electrode, a gate wiring upper structure provided in contact with the gate electrode, and a side wall spacer, the side wall spacer is comprised of one kind or two or more kinds of inorganic compound insulating layers, and at least one kind of the inorganic compound insulating layer is comprised of silicon oxynitride with a nitrogen content ranging from 30 to 70%.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: December 30, 2008
    Assignee: Elpida Memory Inc.
    Inventor: Fumiki Aiso
  • Patent number: 7351654
    Abstract: A method for producing a semiconductor device includes the steps of forming silicon crystal nuclei on a substrate, depositing first amorphous silicon, depositing second amorphous silicon, and crystallizing the first amorphous silicon and the second amorphous silicon by allowing the crystal nuclei to grow in the solid phase.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: April 1, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Norishiro Komatsu, Fumiki Aiso, Toshiyuki Hirota
  • Publication number: 20080073708
    Abstract: A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device may include, but is not limited to, a semiconductor substrate and a third array of semiconductor elements. The semiconductor substrate may include a first array of separate grooves, a second array of separate active regions, and at least an isolating region, the isolating region separating the separate active regions from each other. Each separate groove extends in the separate active region and does not extend over the isolating region. The third array of semiconductor elements is provided on the semiconductor substrate. Each of the semiconductor elements has an electrically conductive portion that is provided in the separate groove. The semiconductor element may be a trench gate transistor, and the electrically conductive portion may be a gate electrode.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 27, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Fumiki AISO
  • Publication number: 20070238310
    Abstract: A semiconductor device manufacturing method includes: a process of forming an isolation trench on the surface of a semiconductor substrate; a process of forming a thermally-oxidized film on the surface of the isolation trench; a process of depositing a silicon oxynitride film on the semiconductor substrate via the thermally-oxidized film; a process of heat-treating the silicon oxynitride film in an oxidizing atmosphere; and a process of etching the top of the thermally-oxidized film and the heat-treated silicon oxynitride film.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 11, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yo Matsuda, Fumiki Aiso, Toshiyuki Hirota
  • Publication number: 20070224763
    Abstract: In a method of manufacturing a semiconductor device, a trench is formed to have an upper quadrangular section and a lower circular section which is formed through a hydrogen annealing process, to extend in a depth direction of a semiconductor substrate. An insulating film is formed on a surface of the trench and a surface of the semiconductor substrate. A conductive film is formed to fill the trench whose surface is covered with the an insulating film. Source/drain regions are formed on both sides of the trench.
    Type: Application
    Filed: March 14, 2007
    Publication date: September 27, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroyuki Fujimoto, Yasuhiko Ueda, Fumiki Aiso, Yuki Koga