Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element.

Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element.

Abstract: A switch 100 includes a plurality of ports 101 for exchanging data. A shared memory 102 enables the exchange of data between first and second ones of the ports 101 and includes an array 202 of memory cells arranged as a plurality of rows and a single column having width equal to a predetermined word-width and circuitry 202, 204, 206, 208 for writing selected data presented at the first one of the ports 101 to a selected row in the array as a word of the predetermined word-width during a first time period and for reading the selected data from the selected row as a word of the predetermined wordwidth during a second time period for output at a second one of the ports 101.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: A flash controller reliably stores data in NAND FLASH by encoding data using an encoding algorithm, and storing that data across multiple pages of the memory. In one embodiment, true data is accepted by the controller, and the controller in turn creates coded data that is the bit-for-bit complement of the true data. The true data and the coded data are then written to the NAND FLASH on a page by page basis. A property of the coding techniques used is that, in at least some cases, detected errors can be corrected.

Abstract: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: A memory subsystem and method for loading and storing data at memory addresses of the subsystem. The memory subsystem is functionally connected to a processor and has a first mode of address encryption to convert logical memory addresses generated by the processor into physical memory addresses at which the data are stored in the memory subsystem. The memory subsystem is adapted to pull low a write enable signal to store data in the memory subsystem and to pull high the write enable signal to load data in the memory subsystem, wherein if pulled high the write enable signal alters the address encryption from the first mode to a second mode. The memory subsystem is adapted to be coupled to a local hardware device which supplies a key that acts upon the address encryption of the memory subsystem.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the determining and the writing may be performed at a granularity level finer than a data word. In embodiments, the bit to be written may be determined by error correction.

Abstract: A system and method is described for enhancing data security in a broad range of electronic systems through encryption and decryption of addresses in physical memory to which data is written and from which data is read. It can be implemented through software, hardware, firmware or any combination thereof. Implementation in Digital Rights Management execution using the invention reduces cost, enhances performance, and provides additional transactional security.

Abstract: Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor is described herein. Embodiments may include memory devices and systems that have plurality of row lines, column lines, and memory cells each of which comprising an access transistor, a storage capacitor and a CMOS-compatible non-volatile storage element connected in series. The CMOS-compatible non-volatile storage element may store charges corresponding to a binary value. The node located between the CMOS-compatible non-volatile storage element and the storage capacitor may be defined as a storage node. During read operation, a cell may be selected, and the voltage at the storage node of the cell may be sensed at the corresponding column line, and the binary value may be determined based on at least the sensed voltage.

Abstract: Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells.

Abstract: Embodiments provide systems, methods, and apparatuses with a plurality of row lines and column lines arranged in a matrix, and at least one memory cell having an access transistor and a CMOS-compatible non-volatile storage element coupled to the access transistor in series. The CMOS-compatible non-volatile storage element includes a node and is configured to hold a charge corresponding to a n-bit binary value where n is an integer greater than 1. The access transistor has a word line gate coupled to a row line, a first node coupled to a column line, a second node coupled to a storage node, with the storage node connected to said node of the CMOS-compatible non-volatile storage element. Access circuitry coupled to the memory cell is configured to activate the memory cell and sense a resulting current corresponding to the n-bit binary value.

Abstract: Digital memory devices and systems, as well as methods of operating digital memory devices, that include access circuitry to access a first subset of a plurality of memory cells associated with a current access address during a current access cycle and precharge circuitry, disposed in parallel relative to the access circuitry, to precharge in full or in part a second subset of the plurality of memory cells associated with a next precharge address during the current access cycle.

Abstract: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element.