Abstract: Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a detector is employed. The detector shuts off power to the I/O driver if the digital value being presented is the same as a previously presented digital value.

Abstract: Embodiments provide methods, apparatuses and systems including a plurality of memory cells configured to store bit values while being powered at a power-saving voltage lower than a normal-operation voltage during operation of a host apparatus, and power circuitry coupled to the plurality of memory cells. The power circuitry is configured to selectively power a first subset of the plurality of memory cells at the normal-operation voltage during operation of the host apparatus while concurrently powering a second subset of the plurality of memory cells at the power-saving voltage. The first and second subsets being different subsets of the memory cells.

Abstract: Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the determining and the writing may be performed at a granularity level finer than a data word. In embodiments, the bit to be written may be determined by error correction.

Abstract: Digital memory devices and systems, as well as methods of operating digital memory devices, that include a multivalue memory cell with a first and a second gating transistor arranged in parallel, having a first and a second node, respectively, coupled to a storage element, and sensing circuitry coupled to a third and a fourth node of the first and second gating transistors, respectively, to sense a stored voltage of the memory cell. In embodiments, the first and second gating transistors are configured to activate at different threshold voltage levels.

Abstract: A system and method is described for enhancing data security in a broad range of electronic systems through encryption and decryption of addresses in physical memory to which data is written and from which data is read. It can be implemented through software, hardware, firmware or any combination thereof. Implementation in Digital Rights Management execution using the invention reduces cost, enhances performance, and provides additional transactional security.

Abstract: A method and architecture that overcomes the problem of latency-caused performance degradation of electronic memory systems. The method involves a “Posted Precharge,” by which an external command for Precharge is given as early as possible, such as immediately following a Read command. The execution of the Precharge is delayed by a precharge counter until all Read/Write commands are completed. By posting a precharge command on a bus at the first available opportunity, multiple pages can be open on the same bank of a memory device. As a result, access latencies are significantly reduced and efficiency of bus in electronic memory systems is significantly improved.

Abstract: Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a subset of memory cells, where the subset of memory cells contains fewer memory cells than the device as a whole and where the device selectively precharges, in response to the received command, only a subset of bit lines associated with the subset of memory cells.

Abstract: Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells.

Abstract: The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.

Abstract: The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.

Abstract: The invention describes and provides multiple data path memories and systems utilizing such memories. Enhanced data throughput and bandwidth, while substantially simultaneously providing improved bus utilization, are some of the benefits. In peer-to-peer connected systems, multiple bank/access block/sector/sub-array with random data throughput can also be realized. A memory including a plurality of independently accessible memory banks, a READ BUS for selectively reading to a selected on of the memory banks, and a WRITE BUS independent of the READ BUS for selectively writing to a selected one of the memory banks, is described.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: The present invention is directed to a built-in solution for soft error protection by forming an epitaxial layer with a graded dopant concentration. By grading a dopant concentration, starting from a first dopant concentration and ending with a second dopant concentration at the device layer, usually determined by the characteristics of the device to be built in the device layer, a constant electric field (?-field) results from the changing dopant concentration. The creation of this ?-field influences the stray, unwanted charges (or transient charges) away from critical device components. Charges that are created in the epitaxial layer are sweep downward, toward, and sometimes into, the substrate where they are absorbed, thus unable to cause a soft error in the device.

Abstract: The invention describes and provides multiple data path memories and systems utilizing such memories. Enhanced data throughput and bandwidth, while substantially simultaneously providing improved bus utilization, are some of the benefits. In peer-to-peer connected systems, multiple bank/access block/sector/sub-array with random data throughput can also be realized. A memory including a plurality of independently accessible memory banks, a READ BUS for selectively reading to a selected on of the memory banks, and a WRITE BUS independent of the READ BUS for selectively writing to a selected one of the memory banks, is described.

Abstract: The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.

Abstract: The present invention is directed to a built-in solution for soft error protection by forming an epitaxial layer with a graded dopant concentration. By grading a dopant concentration, starting from a first dopant concentration and ending with a second dopant concentration at the device layer, usually determined by the characteristics of the device to be built in the device layer, a constant electric field (&egr;-field) results from the changing dopant concentration. The creation of this &egr;-field influences the stray, unwanted charges (or transient charges) away from critical device components. Charges that are created in the epitaxial layer are sweep downward, toward, and sometimes into, the substrate where they are absorbed, thus unable to cause a soft error in the device.

Abstract: A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic random access 407.

Abstract: A memory 200 comprises a first memory bank 201a including an array of memory cells 202a and row and column address circuitry 203a, 205a for addressing a location within the array 202a. The memory further includes a second memory bank 201b including an array of memory cells 202b and row and column address circuitry 203b, 205b for addressing locations within the array 202b. Row and address column circuitry 203, 206, 207 is included for selectively pipelining a plurality of serially received words of address bits to the banks. Furthermore, circuitry places the memory into priority precharge in response to a priority signal, where the priority precharge terminates a current access to the memory and some addresses required for a priority access are selectively pipelined during priority precharge.

Abstract: Memory 900 includes an array 401 of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines. A first port (PORT1) is utilized for accessing selected ones of the memory cells using the first wordline and the first bitline of corresponding ones of the rows and columns, first port (PORT1) associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses via first processing device 101 using a time base and an access-type required by such first processing device. A second port (PORT2) is utilized for accessing selected ones of the memory cells using the second wordline and the second bitline of corresponding ones of the rows and columns, second port (PORT2) associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a second processing device 1002.

Abstract: A memory 1300 including an array of rows and columns of memory cells 501 is disclosed. For each column, first and second interdigitated bitlines 1301, 1303 are coupled to the cells of the column. The first bitlines 1301 has an end coupled to a sense amplifier 1302 at a first boundary of the array and a second bitline 1303 has an end coupled to a second sense amplifier at a second boundary of the array, the first and second boundaries being spaced apart by the array. Control circuitry 508 precharges the first bitlines 1301 of the columns of the array substantially simultaneous to an access to the array through the second bitlines 1303 of selected columns of the array.