Patents by Inventor Garo J. Derderian

Garo J. Derderian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090127105
    Abstract: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.
    Type: Application
    Filed: January 12, 2009
    Publication date: May 21, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Garo J. Derderian, Donald L. Westmoreland, Stefan Uhlenbrock
  • Patent number: 7527693
    Abstract: The invention includes a deposition system having a reservoir for containment of a metastable specie connected to a deposition chamber. The system includes a metastable specie generating catalyst within the reservoir. The invention also includes an atomic layer deposition apparatus having a deposition chamber that contains a substrate platform, first and second inlets and a dispersion head positioned between the inlets and the substrate platform. The ALD apparatus includes first and second metastable specie containment reservoirs in fluid communication with the deposition chamber through the inlets. One or more sources of carrier gas are configured to deliver carrier gas through at least one of the inlets. The invention also includes an atomic layer deposition method.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: May 5, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7498057
    Abstract: A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the substrate effective to deposit a layer onto the substrate. During such providing, a material adheres to the chamber surface. Reactive purge gas is emitted to the deposition chamber from the purge gas inlets effective to form a reactive gas curtain over the chamber surface and away from the substrate, with such reactive gas reacting with such adhering material. Further implementations are contemplated.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: March 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 7482037
    Abstract: A method of forming a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: January 27, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Donald L. Westmoreland, Stefan Uhlenbrock
  • Patent number: 7465627
    Abstract: This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen comprising material on the first capacitor electrode material. The dielectric silicon and nitrogen comprising material is exposed to an aqueous fluid comprising a base and an oxidizer. The aqueous fluid has a pH greater than 7.0. After the exposing to the aqueous fluid, an aluminum oxide comprising capacitor dielectric material is deposited over the first capacitor electrode material. A second capacitor electrode material is formed over the aluminum oxide comprising capacitor dielectric material. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: December 16, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Kevin R. Shea
  • Patent number: 7465650
    Abstract: This invention includes methods of forming plugs containing polysilicon, and methods of forming FLASH memory circuitry. In one implementation, a method of forming a plug containing polysilicon includes providing a substrate having an opening formed therein. Polysilicon is formed within the opening to less than fill the opening. The polysilicon within the opening is exposed to an atmosphere containing H2 and a temperature of at least 500° C. After such exposing, metal is formed within the opening over the polysilicon. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: December 16, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Garo J. Derderian
  • Publication number: 20080251828
    Abstract: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.
    Type: Application
    Filed: September 17, 2007
    Publication date: October 16, 2008
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej Singh Sandhu
  • Patent number: 7431966
    Abstract: The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed onto the substrate to form a first species monolayer within the deposition chamber from a gaseous precursor. The chemisorbed first species is contacted with remote plasma oxygen derived at least in part from at least one of O2 and O3 and with remote plasma nitrogen effective to react with the first species to form a monolayer comprising an oxide of a component of the first species monolayer. The chemisorbing and the contacting with remote plasma oxygen and with remote plasma nitrogen are successively repeated effective to form porous oxide on the substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: October 7, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Shuang Meng, Danny Dynka
  • Publication number: 20080241386
    Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
    Type: Application
    Filed: May 5, 2008
    Publication date: October 2, 2008
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 7429541
    Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: September 30, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Chris W. Hill
  • Patent number: 7411254
    Abstract: The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a crystalline form TiN, WN, elemental form W, or SiC comprising layer is deposited onto the exposed elemental silicon containing surface to a thickness no greater than 50 Angstroms. Such layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal rich silicide is deposited onto the plasma exposed layer.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Cem Basceri
  • Patent number: 7410898
    Abstract: In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Shuang Meng, Garo J. Derderian
  • Patent number: 7402498
    Abstract: The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate. A trench isolation material is formed within the isolation trench and over the masking material outside of the trench effective to overfill the isolation trench. The trench isolation material is polished at least to an outermost surface of the at least one of tungsten, titanium nitride and amorphous carbon of the masking material. The at least one of tungsten, titanium nitride and amorphous carbon is/are etched from the substrate. Other implementations and aspects are contemplated.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: July 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, H. Montgomery Manning
  • Patent number: 7393783
    Abstract: The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The desired layers can be formed by initially depositing a metal-containing layer which comprises metal and halogen atoms. Subsequently, trialkylaluminum is utilized to remove the halogen atoms from the layer. The layer remaining after removal of the halogen atoms can comprise, consist essentially, or consist of any suitable metal, and in particular aspects can consist essentially of, or consist of, titanium or titanium/aluminum.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: July 1, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Garo J. Derderian
  • Patent number: 7393562
    Abstract: A method of providing material into a deposition chamber is provided. A reservoir is in fluid communication with the deposition chamber. A metastable specie is provided and contained within the reservoir prior to flowing the metastable specie from the reservoir into the deposition chamber. For atomic layer deposition, the metastable specie can be purged from the containment reservoir and the metastable specie can be compressed into the reaction chamber from the reservoir. A portion of the metastable specie is deposited onto a substrate.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: July 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7387685
    Abstract: Reactors for vapor deposition of materials onto a microelectronic workpiece, systems that include such reactors, and methods for depositing materials onto microelectronic workpieces. In one embodiment, a reactor for vapor deposition of a material comprises a reaction chamber and a gas distributor. The reaction chamber can include an inlet and an outlet. The gas distributor is positioned in the reaction chamber. The gas distributor has a compartment coupled to the inlet to receive a gas flow and a distributor plate including a first surface facing the compartment, a second surface facing the reaction chamber, and a plurality of passageways. The passageways extend through the distributor plate from the first surface to the second surface. Additionally, at least one of the passageways has at least a partially occluded flow path through the plate.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Craig M. Carpenter, Allen P. Mardian, Ross S. Dando, Kimberly R. Tschepen, Garo J. Derderian
  • Patent number: 7378354
    Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 27, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 7368381
    Abstract: The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the chamber. The mixture includes a precursor of a desired material within a supercritical fluid. The precursor is relatively reactive under one set of conditions and is relatively non-reactive under another set of conditions. The precursor and supercritical fluid mixture is initially provided in the chamber under the conditions at which the precursor is relatively non-reactive. Subsequently, and while maintaining the supercritical state of the supercritical fluid, the conditions within the reaction chamber are changed to the conditions under which the precursor is relatively reactive. The precursor reacts to form the desired material, and at least some of the desired material forms a film on the substrate.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J Derderian, Cem Basceri
  • Patent number: 7368382
    Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 7361614
    Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: April 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Chris W. Hill