Patents by Inventor Garo J. Derderian

Garo J. Derderian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7329615
    Abstract: This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed to form a first species monolayer onto the substrate within the deposition chamber from a gaseous first precursor. The chemisorbed first species is contacted with a gaseous second precursor effective to react with the first species to form an oxide of a component of the first species monolayer. The contacting at least in part results from flowing O3 to the deposition chamber, with the O3 being at a temperature of at least 170° C. at a location where it is emitted into the deposition chamber. The chemisorbing and the contacting are successively repeated to form an oxide comprising layer on the substrate. Additional aspects and implementations are contemplated.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: February 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Demetrius Sarigiannis, Shuang Meng
  • Patent number: 7326984
    Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: February 5, 2008
    Assignee: Micron Technology, Inc
    Inventors: Cem Basceri, Garo J. Derderian
  • Patent number: 7323412
    Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: January 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7323231
    Abstract: One aspect of the invention is directed toward a method of forming a conductive layer on a microfeature workpiece. In one embodiment, the method comprises placing a microfeature workpiece in a vapor reaction chamber, depositing an electrically conductive material onto the microfeature workpiece in a vapor deposition process by flowing a gas into a plasma zone of the vapor deposition chamber and transmitting energy into the plasma zone via a transmitting window. The energy transmitted through the window and into the plasma zone produces plasma from the gas. The plasma produced from the gas forms a conductive layer on the workpiece and a residual film on the window. This embodiment of the method further includes changing the residual film on the window to have a reduced transmissivity to the energy.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: January 29, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Garo J. Derderian
  • Patent number: 7323738
    Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: January 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian
  • Patent number: 7312163
    Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7311942
    Abstract: A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Cem Basceri, Donald L. Westmoreland
  • Patent number: 7303991
    Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: December 4, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 7282239
    Abstract: In one embodiment, the system includes a gas supply assembly having a first gas source, a first gas conduit coupled to the first gas source, a first valve assembly, a reaction chamber, and a gas distributor carried by the reaction chamber. The first valve assembly includes first and second valves that are in fluid communication with the first gas conduit. The first and second valves are configured in a parallel arrangement so that the first gas flows through the first valve and/or the second valve.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Shuang Meng, Garo J. Derderian
  • Patent number: 7279396
    Abstract: The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate. A trench isolation material is formed within the isolation trench and over the masking material outside of the trench effective to overfill the isolation trench. The trench isolation material is polished at least to an outermost surface of the at least one of tungsten, titanium nitride and amorphous carbon of the masking material. The at least one of tungsten, titanium nitride and amorphous carbon is/are etched from the substrate. Other implementations and aspects are contemplated.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: October 9, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, H. Montgomery Manning
  • Patent number: 7279732
    Abstract: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: October 9, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej Singh Sandhu
  • Patent number: 7271053
    Abstract: A method of forming a capacitor includes forming a first conductive capacitor electrode layer over a substrate. The first electrode layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a capacitor dielectric layer onto the outer surface. A conductive capacitor electrode layer is formed over the capacitor dielectric layer. A method of forming an electronic device includes forming a conductive layer over a substrate. The conductive layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a dielectric layer onto the outer surface.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: September 18, 2007
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Garo J. Derderian, Chris M. Carlson
  • Patent number: 7271077
    Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: September 18, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Eugene Marsh, Brian Vaartstra, Paul J. Castrovillo, Cem Basceri, Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7256123
    Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: August 14, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7253104
    Abstract: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7250380
    Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: July 31, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Chris W. Hill
  • Patent number: 7250378
    Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: July 31, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Chris W. Hill
  • Patent number: 7247561
    Abstract: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: July 24, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Cem Basceri, Christopher W. Hill, Garo J. Derderian
  • Patent number: 7217615
    Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: May 15, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7204885
    Abstract: Chemical vapor deposition systems include elements to preheat reactant gases prior to reacting the gases to form layers of a material on a substrate, which provides devices and systems with deposited layers substantially free of residual compounds from the reaction process. Heating reactant gases prior to introduction to a reaction chamber may be used to improve physical characteristics of the resulting deposited layer, to improve the physical characteristics of the underlying substrate and/or to improve the thermal budget available for subsequent processing.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: April 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gordon Morrison