Patents by Inventor Garo J. Derderian

Garo J. Derderian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7189642
    Abstract: In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: March 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Shuang Meng, Garo J. Derderian
  • Patent number: 7176118
    Abstract: The invention includes methods of forming regions of differing composition over a substrate. A first material having a pattern of at least one substantially amorphous region and at least one substantially crystalline region is provided over the substrate. The at least one substantially amorphous region of the first material is replaced with a second material, while the at least one substantially crystalline region is not replaced. The invention also includes a circuit construction comprising an electrically conductive material extending within openings in a substantially crystalline electrically insulative material, and in which the electrically conductive material corresponds to quantum dots.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: February 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian
  • Patent number: 7166885
    Abstract: The invention includes semiconductor devices. In one implementation, semiconductor device includes a first conductive material. A first layer of a dielectric material is over the first conductive material. A second layer of the dielectric material is on the first layer. A second conductive material is over the second layer of the dielectric material. A device in accordance with an implementation of the invention can include a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, Garo J. Derderian
  • Patent number: 7164165
    Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: January 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian
  • Patent number: 7157385
    Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: January 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Chris W. Hill
  • Patent number: 7153751
    Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian
  • Patent number: 7150789
    Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. After forming the first monolayer, a reactive intermediate gas is flowed to the substrate within the deposition chamber. The reactive intermediate gas is capable of reaction with an intermediate reaction by-product from the first precursor flowing under conditions of the reactive intermediate gas flowing. After flowing the reactive intermediate gas, a second precursor gas is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: December 19, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Paul J. Castovillo, Cem Basceri, Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7128787
    Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. After forming the first monolayer, a reactive intermediate gas is flowed to the substrate within the deposition chamber. The reactive intermediate gas is capable of reaction with an intermediate reaction by-product from the first precursor flowing under conditions of the reactive intermediate gas flowing. After flowing the reactive intermediate gas, a second precursor gas is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: October 31, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Paul J. Castovillo, Cem Basceri, Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7122422
    Abstract: This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen comprising material on the first capacitor electrode material. The dielectric silicon and nitrogen comprising material is exposed to an aqueous fluid comprising a base and an oxidizer. The aqueous fluid has a pH greater than 7.0. After the exposing to the aqueous fluid, an aluminum oxide comprising capacitor dielectric material is deposited over the first capacitor electrode material. A second capacitor electrode material is formed over the aluminum oxide comprising capacitor dielectric material. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Kevin R. Shea
  • Patent number: 7119034
    Abstract: This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed to form a first species monolayer onto the substrate within the deposition chamber from a gaseous first precursor. The chemisorbed first species is contacted with a gaseous second precursor effective to react with the first species to form an oxide of a component of the first species monolayer. The contacting at least in part results from flowing O3 to the deposition chamber, with the O3 being at a temperature of at least 170° C. at a location where it is emitted into the deposition chamber. The chemisorbing and the contacting are successively repeated to form an oxide comprising layer on the substrate. Additional aspects and implementations are contemplated.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Demetrius Sarigiannis, Shuang Meng
  • Patent number: 7118783
    Abstract: CVD, ALD, and other vapor processes used in processing semiconductor workpieces often require volatilizing a liquid or solid precursor. Certain embodiments of the invention provide improved and/or more consistent volatilization rates by moving a reaction vessel. In one exemplary embodiment, a reaction vessel is rotated about a rotation axis which is disposed at an angle with respect to vertical. This deposits a quantity of the reaction precursor on an interior surface of the vessel's sidewall which is exposed to the headspace as the vessel rotates. Other embodiments employ drivers adapted to move the reaction vessel in other manners, such as a pendulum arm to oscillate the vessel along an arcuate path or a mechanical linkage which moves the vessel along an elliptical path.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Craig M. Carpenter, Ross S. Dando, Dan Gealy, Garo J. Derderian, Allen P. Mardian
  • Patent number: 7109113
    Abstract: A solid source precursor material is delivered to a deposition chamber in vaporized form by utilizing a solid source precursor delivery system having either single or multiple stations(s) having a collection/delivery reservoir that is an intermediate stage between a solid source reservoir and a processing deposition chamber. Each collection/delivery reservoir transitions between a collection phase of the solid precursor and the delivery stage of the vaporized precursor during the deposition of a film.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: September 19, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Garo J. Derderian
  • Patent number: 7109542
    Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: September 19, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7105441
    Abstract: Chemical vapor deposition systems include elements to preheat reactant gases prior to reacting the gases to form layers of a material on a substrate, which provides devices and systems with deposited layers substantially free of residual compounds from the reaction process. Heating reactant gases prior to introduction to a reaction chamber may be used to improve physical characteristics of the resulting deposited layer, to improve the physical characteristics of the underlying substrate and/or to improve the thermal budget available for subsequent processing. One example includes the formation of a titanium nitride layer substantially free of ammonium chloride using reactant gases containing a titanium tetrachloride precursor and a ammonia precursor.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gordon Morrison
  • Patent number: 7094690
    Abstract: A deposition method includes, at a first temperature, contacting a substrate with a surface activation agent and adsorbing a first layer over the substrate. At a second temperature greater than the first temperature, the first layer may be contacted with a first precursor, chemisorbing a second layer at least one monolayer thick over the substrate. The first layer may enhance a chemisorption rate of the first precursor compared to the substrate without the surface activation agent adsorbed thereon. One deposition apparatus includes a deposition chamber with a precursor gas dispenser in a contacting zone and a cooling gas dispenser in a cooling zone. A substrate chuck moves by linear translational motion from the contacting zone to the cooling zone. The substrate chuck includes a substrate lift that positions a deposition substrate at an elevation above a heated surface of the substrate chuck when dispensing a cooling gas or surface activation agent.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: August 22, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Garo J. Derderian, Guy T. Blalock, Terry L. Gilton
  • Patent number: 7087535
    Abstract: A deposition method includes contacting a substrate with a first initiation precursor and forming a first portion of an initiation layer on the substrate. At least a part of the substrate is contacted with a second initiation precursor different from the first initiation precursor and a second portion of the initiation layer is formed on the substrate. The substrate may be simultaneously contacted with a plurality of initiation precursors, forming on the substrate and initiation layer comprising components derived from each of the plurality of initiation precursors. An initiation layer may be contacted with a deposition precursor, forming a deposition layer on the initiation layer. The deposition layer may be contacted with a second initiation precursor different from the first initiation precursor forming a second initiation layer over the substrate.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 8, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7087525
    Abstract: The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the chamber. The mixture comprises a precursor of a desired material within a supercritical fluid. The precursor is relatively reactive under one set of conditions and is relatively non-reactive under another set of conditions. The precursor and supercritical fluid mixture is initially provided in the chamber under the conditions at which the precursor is relatively non-reactive. Subsequently, and while maintaining the supercritical state of the supercritical fluid, the conditions within the reaction chamber are changed to the conditions under which the precursor is relatively reactive. The precursor reacts to form the desired material, and at least some of the desired material forms a film on the substrate.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: August 8, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri
  • Patent number: 7078757
    Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: July 18, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian
  • Patent number: 7071098
    Abstract: In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: July 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Shuang Meng, Garo J. Derderian
  • Patent number: 7071508
    Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: July 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian