Abstract: A method includes forming first sacrificial layers and first channel layers alternately stacked over a substrate; forming second channel layers and second sacrificial layers alternately stacked over the first sacrificial layers and the first channel layers, in which the second channel layers are made of a first semiconductive oxide; performing an etching process to remove portions of the first sacrificial layers and the second sacrificial layers; forming a gate structure in contact with the first channel layers and the second channel layers; forming first source/drain contacts on opposite sides of the gate structure and electrically connected to the first channel layers; and forming second source/drain contacts on the opposite sides of the gate structure and electrically connected to the second channel layers.

Abstract: A method includes forming a first dielectric layer over a substrate; forming a first transistor over a first side of the first dielectric layer; removing the substrate to expose a second side of the first dielectric layer opposite to the first side of the second dielectric layer; and forming a second transistor over the second side of the first dielectric layer. Forming the first transistor includes forming a semiconductor layer over the first side of the first dielectric layer; forming a first gate structure over the semiconductor layer; and forming source/drain epitaxy structures on opposite sides of the first gate structure. Forming the second transistor includes forming a semiconductive oxide layer over the second side of the first dielectric layer; forming a second gate structure over the semiconductive oxide layer; and forming source/drain contacts over the semiconductive oxide layer and on opposite sides of the second gate structure.

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

Abstract: A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.

Abstract: A semiconductor includes a ferroelectric layer, a first semiconductor layer, a first gate, a second semiconductor layer, a second gate and contact structures. The ferroelectric layer has a first surface and a second surface opposite to the first surface. The first semiconductor layer is disposed on the first surface of the ferroelectric layer. The first gate is disposed on the first semiconductor layer over the first surface. The second semiconductor layer is disposed on the second surface of the ferroelectric layer. The second gate is disposed on the second semiconductor layer over the second surface. The contacts structures are connected to the first semiconductor layer and the second semiconductor layer.

Abstract: A transistor, integrated semiconductor device and methods of making are disclosed. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

Abstract: A device and methods of forming the same are described. The device includes a substrate, source/drain regions disposed over the substrate, a ferroelectric layer disposed over the substrate, a gate electrode in contact with the ferroelectric layer, a first conductive contact disposed at a first end of the gate electrode, and a second conductive contact disposed at a second end opposite the first end of the gate electrode. The first and second conductive contacts are configured to allow a current to flow from the first conductive contact through the gate electrode to the second conductive contact.

Abstract: A semiconductor device includes a channel layer, source/drain contacts, and first barrier liners. The channel layer includes an oxide semiconductor material. The source/drain contacts are disposed in electrical contact with the channel layer. The first barrier liners surround the source/drain contacts, respectively, and include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners to the channel layer.

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Abstract: A semiconductor device includes an oxide semiconductor stack, a first gate, a first contact structure, and a second contact structure. The oxide semiconductor stack includes an n-type oxide semiconductor layer and a p-type oxide semiconductor layer stacked on each other. The first gate is over the oxide semiconductor stack. The first contact structure and the second contact structure are at opposite sides of the first gate and electrically connected to the oxide semiconductor stack.

Abstract: A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

Abstract: A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.

Abstract: The present disclosure relates to an integrated chip including a channel structure on a first substrate. A gate electrode overlies the channel structure. A first source/drain structure abuts the channel structure and is offset from the gate electrode. A conductive structure is disposed on the first substrate and underlies the first source/drain structure. A first contact extends from the first source/drain structure to the conductive structure.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Abstract: A semiconductor structure includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a logic structure overlying a semiconductor substrate of the semiconductor device. The logic structure includes a plurality of logic cells. The semiconductor device includes one or more interconnection layers, overlying the logic structure, in a Back End of Line (BEOL) structure of the semiconductor device. The semiconductor device includes a non-volatile memory array, including a plurality of memory cells, overlying the logic structure and the one or more interconnection layers, wherein the non-volatile memory array at least one of overlies or is within the BEOL structure.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a source/drain structure, a first buried power line, a contact, a first through substrate via (TSV), and a second TSV. The substrate has a well region extending a front-side surface of the substrate into the substrate. The semiconductor fin is on the well region. The source/drain structure is on the semiconductor fin. The first buried power line is electrically coupled to the source/drain structure on the first semiconductor fin. The first buried power line has a length extending along a lengthwise direction of the first semiconductor fin and a height extending within the well region. The first TSV extends from a back-side surface of the substrate through the substrate to the first buried power line. The second TSV extends from the back-side surface of the substrate to the well region.

Abstract: A semiconductor device is provided. The semiconductor device includes a memory structure including a first transistor channel, a gate structure overlying the first transistor channel, and a second transistor channel overlying the gate structure. The gate structure includes a control gate.