Abstract: A security circuit comprising including a sensor located remotely from a central alarm handler and configured to sense an attack, and a phase-change memory cell coupled to and located remotely with the sensor, and configured to store an alarm event when the attack is sensed.

Abstract: A method for monitoring the correct operations of a data processing device including changing a subsystem from an authorized state to an unauthorized state, executing the partial operating sequence, and resetting any subsystem state from the unauthorized state to the authorized state.

Abstract: A method for monitoring the correct operations of a data processing device including changing a subsystem from an authorized state to an unauthorized state, executing the partial operating sequence, and resetting any subsystem state from the unauthorized state to the authorized state.

Abstract: Circuit arrangement having a chip card controller with connections which can be used to access the chip card controller in accordance with the ISO standard and which are connected or can be connected to an ISO interface. The connections include at least one first connection, which can be connected to the ISO interface via a switch device. In addition, the circuit arrangement includes a further controller with at least one controller connection which is coupled to the switch device such that the first connection of the chip card controller can be connected to the controller connection via the switch device. The switch device can be switched between a first and a second state, where in the first state the first connection of the chip card controller is decoupled from the controller connection and is connected to the ISO interface, and where in the second state the first connection of the chip card controller is decoupled from the ISO interface and is connected to the controller connection.

Abstract: A device for generating a pseudorandom sequence of numbers includes a feedforward coupler, which has a plurality of memory units, and a feedback coupler connected between an input and an output of the feedforward coupler. The feedback coupler includes a changeable feedback characteristic and is embodied to change the feedback characteristic depending on a state of a memory unit of the plurality of memory units of the feedforward coupler.

Abstract: A pseudorandom number generator includes a unit for providing a number of 2n sequences of numbers, n being greater than or equal to 2. The sequences of numbers are combined by a unit such that at first all the sequences of numbers are combined with one another in an intermediate processing stage to obtain an intermediate processing sequence, and that subsequently a subgroup of k sequences of numbers is combined with the intermediate processing sequence in a final processing stage to obtain the output sequence.

Abstract: Circuit arrangement having a transmitter and a receiver coupled to the transmitter via N signal lines, wherein a useful information signal is exchanged between the transmitter and the receiver via M randomly selectable signal lines, N being greater than M.

Abstract: A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump command. The processor has a command processor, which is adapted in the mother program upon occurrence of the sub-program jump command, to extract back-up information about data required in the mother program after processing the sub-program from the sub-program jump command, to back-up data required in the mother program after execution of the sub-program based on the back-up information, to extract a destination address from the sub-program jump command, which refers to the sub-program, and to effect the continuation of the processing of the program with the sub-program based on the destination address.

Abstract: Apparatus for contactless data transmission according to a predetermined transmission protocol providing control information and payload for a data transmission, with a near field communicator and an interface connected to the near field communicator, the interface being operative to exchange, using a first protocol, data with the near field communicator for the contactless transmission. In this context, the first protocol provides a transmission of control information and payload, the payload of the first protocol including the control information and the payload of the predetermined protocol. The apparatus further includes a module coupled to the interface and being operative to exchange, using the payload of the first protocol, the control information and the payload of the predetermined transmission protocol for the data exchanged contactlessly by the near field communicator.

Abstract: A method for monitoring the correct operations of a data processing device including changing a subsystem from an authorized state to an unauthorized state, executing the partial operating sequence, and resetting any subsystem state from the unauthorized state to the authorized state.

Abstract: A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic components is connected to the output of the other logic component. The second inputs of each of the logic components are connected to a control line. The first and second logic components are embodied such that when a control signal having a first level is applied to the control line at the respective output, a signal is output which has an output level that is inverted with respect to the level of the signal present at the respective first input, and when a control signal having a second level is applied to the control line at the respective output, a signal is output which has a predetermined level independent of the level of the signal present at the respective first input.

Abstract: Circuit arrangement having a chip card controller with connections which can be used to access the chip card controller in accordance with the ISO standard and which are connected or can be connected to an ISO interface. The connections include at least one first connection, which can be connected to the ISO interface via a switch device. In addition, the circuit arrangement includes a further controller with at least one controller connection which is coupled to the switch device such that the first connection of the chip card controller can be connected to the controller connection via the switch device. The switch device can be switched between a first and a second state, where in the first state the first connection of the chip card controller is decoupled from the controller connection and is connected to the ISO interface, and where in the second state the first connection of the chip card controller is decoupled from the ISO interface and is connected to the controller connection.

Abstract: Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the memory device, an apparatus which has an input and an output, at least one test reference source which can be connected to the input of the apparatus by data stored in the buffer device, and a test apparatus, which is connected to the buffer device and to the output of the apparatus, and which is designed to compare a signal at the output of the apparatus with data stored in the buffer device.

Abstract: A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic components is connected to the output of the other logic component. The second inputs of each of the logic components are connected to a control line. The first and second logic components are embodied such that when a control signal having a first level is applied to the control line at the respective output, a signal is output which has an output level that is inverted with respect to the level of the signal present at the respective first input, and when a control signal having a second level is applied to the control line at the respective output, a signal is output which has a predetermined level independent of the level of the signal present at the respective first input.

Abstract: An encryption unit and decryption unit located in an encryption/decryption device may be used both for encryption and decryption, without their effects canceling each other out when, between the decryption input of the decrypter and the encryption output of the encrypter. An encryption combiner maps the encryption result data block at the encryption output to a mapped encryption result data block according to an encryption combining mapping and is exemplarily used when encrypting. A decryption combiner maps the encryption result data block at the encryption output to an inversely mapped encryption result data block according to a decryption combining mapping which is inverse to the encryption combining mapping and is exemplarily used when decrypting.

Abstract: A device for generating a pseudorandom sequence of numbers includes a feedforward coupler, which has a plurality of memory units, and a feedback coupler connected between an input and an output of the feedforward coupler. The feedback coupler includes a changeable feedback characteristic and is embodied to change the feedback characteristic depending on a state of a memory unit of the plurality of memory units of the feedforward coupler.

Abstract: A parallel data bus having a plurality of bus lines, and a bus mode switching device for switching between data transmission at a high data transmission rate and data transmission at high data integrity.

Abstract: Method and system for operating a cache memory. The method includes the steps of splitting the cache memory into sets, addressing the cache memory using a processor address which is split into at least two fields, and forming one of the fields of the processor address for addressing the cache memory from a combinational logic function on a basis of a modulo N operation, where N corresponds to the number of sets in the cache memory.

Abstract: Communications system having a chip card and at least one chip card communications partner, the chip card having a module for initiating data interchange with the chip card communications partner, and a method for interchanging data between a chip card and a chip card communications partner, the chip card initiating data interchange.

Abstract: A memory arrangement and method for operating the memory arrangement comprising a nonvolatile memory and at least one address translation unit, the nonvolatile memory having memory pages and at least one additional memory page, the memory pages and the additional memory page having physical addresses and the address translation unit translating logically addressable addresses into the physical addresses of the memory pages and of the additional memory page. The nonvolatile memory stores data which make address translation possible within an unaddressable area in the memory pages and in the additional memory page. For the purposes of programming a memory page, a copy of data and a copy of the data of the unaddressable area are stored in a further memory for processing and the data of the unaddressable area are changed. Once programming has been completed, the processed copy of the data and the changed data of the unaddressable area are stored in the additional memory page.