Patents by Inventor Geun Ho Choi
Geun Ho Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127502Abstract: Provided are a font generating system and a font generating method. The font generating system and the font generating method of the present disclosure are provided to include a component decomposer which has at least one character input thereto and decomposes the input character into at least one component, a component converter which converts the at least one component into a component with a predetermined font to generate at least one imaging component, and a component recomposer which recomposes the at least one imaging component to generate a fonted character.Type: ApplicationFiled: February 17, 2023Publication date: April 18, 2024Inventors: Jae Young CHOI, Jang Kyoung PARK, Geun Ho JEONG
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Publication number: 20230361306Abstract: Disclosed is an anode for a lithium secondary battery, and more particularly, an anode comprising a fibrillated binder and a particulate binder.Type: ApplicationFiled: December 2, 2022Publication date: November 9, 2023Inventors: Sang Wook HAN, Geun Ho CHOI, Kyeong Wi PARK, Hyun Jin KIM, Yong Il CHO, Han Nah SONG
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Patent number: 11705182Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.Type: GrantFiled: June 1, 2022Date of Patent: July 18, 2023Assignee: SK hynix Inc.Inventors: Kyung Mook Kim, Woongrae Kim, Geun Ho Choi
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Publication number: 20230187643Abstract: The present embodiments relate to a binder, a composition for manufacturing a dry electrode comprising the same, and a method for manufacturing a dry electrode. In one embodiment, as secondary particles comprising at least one first particle, the binder may be separated from the secondary particles into the at least one first particle when stirred with a dispersion equipment.Type: ApplicationFiled: November 23, 2022Publication date: June 15, 2023Applicants: HYUNDAI MOTOR COMPANY, Kia CorporationInventors: Hyunjin KIM, Hannah SONG, Sangwook HAN, Geun Ho CHOI
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Patent number: 11469747Abstract: A shift register generates a synthesized pulse having a different pulse width according to which one of a first phase pulse and a second phase pulse is inputted, generates an internal shifted synthesized pulse and a shifted synthesized pulse from the synthesized pulse, and generates a detection signal by detecting a pulse width of the internal shifted synthesized pulse. The shift register outputs the shifted synthesized pulse as one of a first shifted phase pulse and a second shifted phase pulse based on the detection signal.Type: GrantFiled: December 15, 2021Date of Patent: October 11, 2022Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Young Hyun Baek
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Publication number: 20220293168Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.Type: ApplicationFiled: June 1, 2022Publication date: September 15, 2022Applicant: SK hynix Inc.Inventors: Kyung Mook KIM, Woongrae KIM, Geun Ho CHOI
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Patent number: 11380383Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.Type: GrantFiled: September 3, 2020Date of Patent: July 5, 2022Assignee: SK hynix Inc.Inventors: Kyung Mook Kim, Woongrae Kim, Geun Ho Choi
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Patent number: 11328756Abstract: A semiconductor system includes a controller configured to output a clock, a command and an address; and a semiconductor device configured to generate a flag signal by detecting an input time of the command, which is input in synchronization with the clock in a write auto-precharge operation based on the command, and configured to generate an internal address for performing the write auto-precharge operation, by serializing the address and then parallelizing the flag signal and the serialized address.Type: GrantFiled: April 13, 2021Date of Patent: May 10, 2022Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Ki Hun Kwon
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Patent number: 11221900Abstract: A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.Type: GrantFiled: October 1, 2019Date of Patent: January 11, 2022Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Sun Myung Choi
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Patent number: 11218151Abstract: A system for performing a phase control operation includes: an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variation, and generate a reference clock by delaying the clock by a second delay variation, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variation which is controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.Type: GrantFiled: August 27, 2020Date of Patent: January 4, 2022Assignee: SK hynix Inc.Inventor: Geun Ho Choi
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Patent number: 11211112Abstract: A semiconductor device includes an internal column control signal generation circuit, a bank address transfer circuit, and a first bank control circuit. The internal column control signal generation circuit generates a column control signal to output an internal column control signal. The bank address transfer circuit receives a bank address to generate an inverted bank address and outputs the bank address and the inverted bank address. The first bank control circuit generates a first bank active signal based on at least one of the bank address and the inverted bank address and latches the first bank active signal based on the internal column control signal to generate a first bank column control signal.Type: GrantFiled: July 2, 2020Date of Patent: December 28, 2021Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Kyung Mook Kim, Woongrae Kim
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Publication number: 20210366535Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.Type: ApplicationFiled: September 3, 2020Publication date: November 25, 2021Applicant: SK hynix Inc.Inventors: Kyung Mook KIM, Woongrae KIM, Geun Ho CHOI
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Publication number: 20210359689Abstract: A system for performing a phase control operation includes: an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variation, and generate a reference clock by delaying the clock by a second delay variation, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variation which is controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.Type: ApplicationFiled: August 27, 2020Publication date: November 18, 2021Applicant: SK hynix Inc.Inventor: Geun Ho CHOI
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Publication number: 20210327478Abstract: A system for performing a phase matching operation includes a controller configured to output a clock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.Type: ApplicationFiled: July 17, 2020Publication date: October 21, 2021Applicant: SK hynix Inc.Inventors: Min Su PARK, Min Gyu PARK, Geun Ho CHOI
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Patent number: 11152044Abstract: A system for performing a phase matching operation includes a controller configured to output a dock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.Type: GrantFiled: July 17, 2020Date of Patent: October 19, 2021Assignee: SK hynix Inc.Inventors: Min Su Park, Min Gyu Park, Geun Ho Choi
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Patent number: 11106237Abstract: A shift register includes a latch clock generation circuit and a clock latch circuit. The latch clock generation circuit generates a latch clock signal and an inverted latch clock signal based on a first internal clock signal, a first inverted internal clock signal, a second internal clock signal, and a second inverted internal clock signal. The clock latch circuit latches a control signal in synchronization with one signal selected from the first internal clock signal, the first inverted internal clock signal, the second internal clock signal, and the second inverted internal clock signal. The clock latch circuit also latches the latched control signal in synchronization with the latch clock signal or the inverted latch clock signal to generate and output a shift control signal.Type: GrantFiled: July 17, 2019Date of Patent: August 31, 2021Assignee: SK hynix Inc.Inventor: Geun Ho Choi
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Publication number: 20210249065Abstract: A semiconductor device includes an internal column control signal generation circuit, a bank address transfer circuit, and a first bank control circuit. The internal column control signal generation circuit generates a column control signal to output an internal column control signal. The bank address transfer circuit receives a bank address to generate an inverted bank address and outputs the bank address and the inverted bank address. The first bank control circuit generates a first bank active signal based on at least one of the bank address and the inverted bank address and latches the first bank active signal based on the internal column control signal to generate a first bank column control signal.Type: ApplicationFiled: July 2, 2020Publication date: August 12, 2021Applicant: SK hynix Inc.Inventors: Geun Ho CHOI, Kyung Mook KIM, Woongrae KIM
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Patent number: 10991405Abstract: A semiconductor device includes a flag shifting circuit and an auto-pre-charge control circuit. The flag shifting circuit generates a first shifted flag signal by shifting a first flag signal by a second latency period, the first flag signal generated based on a first operation clock signal, and configured to generate a second shifted flag signal by shifting a second flag signal by a first latency period, the second flag signal generated based on a second operation clock signal. The auto-pre-charge control circuit generates an auto-pre-charge signal by shifting the first shifted flag signal and the second shifted flag signal by a recovery period based on the first operation clock signal and the second operation clock signal.Type: GrantFiled: May 6, 2020Date of Patent: April 27, 2021Assignee: SK hynix Inc.Inventors: Woongrae Kim, Geun Ho Choi, Kyung Mook Kim
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Patent number: 10891995Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.Type: GrantFiled: July 22, 2019Date of Patent: January 12, 2021Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Seung Wook Oh, Jin Il Chung
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Patent number: 10872645Abstract: A semiconductor device includes a variable delay circuit and an address latch circuit. The variable delay circuit delays a read signal by a delay time to generate a latch control signal during an initialization operation and receives a feedback signal to adjust the delay time for delaying the read signal during the initialization operation. The address latch circuit detects a logic level of a transfer address when the latch control signal is inputted to the address latch circuit and generates the feedback signal.Type: GrantFiled: December 31, 2019Date of Patent: December 22, 2020Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Kyung Mook Kim, Woongrae Kim