Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

Abstract: A semiconductor device includes a variable delay circuit and an address latch circuit. The variable delay circuit delays a read signal by a delay time to generate a latch control signal during an initialization operation and receives a feedback signal to adjust the delay time for delaying the read signal during the initialization operation. The address latch circuit detects a logic level of a transfer address when the latch control signal is inputted to the address latch circuit and generates the feedback signal.

Abstract: A redundancy circuit includes a selection control signal generation circuit and a column control circuit. The selection control signal generation circuit drives an internal node, which is initialized, to generate a selection control signal when a logic level of a latched address signal is different from a logic level of a fuse signal. The column control circuit buffers a pre-column selection signal based on the selection control signal to generate a column selection signal for execution of a column operation of cells or to generate a redundancy column selection signal for execution of the column operation of redundancy cells.

Abstract: A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.

Abstract: A shift register includes a latch clock generation circuit and a clock latch circuit. The latch clock generation circuit generates a latch clock signal and an inverted latch clock signal based on a first internal clock signal, a first inverted internal clock signal, a second internal clock signal, and a second inverted internal clock signal. The clock latch circuit latches a control signal in synchronization with one signal selected from the first internal clock signal, the first inverted internal clock signal, the second internal clock signal, and the second inverted internal clock signal. The clock latch circuit also latches the latched control signal in synchronization with the latch clock signal or the inverted latch clock signal to generate and output a shift control signal.

Abstract: A redundancy circuit includes a selection control signal generation circuit and a column control circuit. The selection control signal generation circuit drives an internal node, which is initialized, to generate a selection control signal when a logic level of a latched address signal is different from a logic level of a fuse signal. The column control circuit buffers a pre-column selection signal based on the selection control signal to generate a column selection signal for execution of a column operation of cells or to generate a redundancy column selection signal for execution of the column operation of redundancy cells.

Abstract: A semiconductor package includes a semiconductor chip including at least one vertical hole that penetrates therethrough in a vertical direction, and a mold covering the semiconductor chip, and including at least one first horizontal hole and at least one second horizontal hole that are formed in a horizontal direction, wherein the first horizontal hole and the second horizontal hole are connected through the vertical hole.

Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

Abstract: A semiconductor device includes a command synthesis circuit synchronized with a first division clock signal to shift a command based on an offset signal and synchronized with a second division clock signal to generate a command synthesis signal from the shifted command. The semiconductor device also includes a strobe control signal synthesis circuit synchronized with the second division clock signal to generate a strobe synthesis signal from a strobe control signal. The semiconductor device further includes a drive control circuit generating a drive control signal from any one of the command synthesis signal and a drive signal based on the strobe synthesis signal.

Abstract: A semiconductor device includes a command synthesis circuit synchronized with a first division clock signal to shift a command based on an offset signal and synchronized with a second division clock signal to generate a command synthesis signal from the shifted command. The semiconductor device also includes a strobe control signal synthesis circuit synchronized with the second division clock signal to generate a strobe synthesis signal from a strobe control signal. The semiconductor device further includes a drive control circuit generating a drive control signal from any one of the command synthesis signal and a drive signal based on the strobe synthesis signal.

Abstract: A semiconductor device includes a control circuit configured to generate a data reset signal which is enabled in response to a reset signal and first and second transfer control signals which are sequentially enabled in synchronization with a divided clock in response to a read signal and a trigger circuit configured to drive a driving signal depending on a logic level of latch data in synchronization with delayed clocks in response to the first and second transfer control signals, the driving signal having a fixed logic level based on the data reset signal being enabled.

Abstract: A semiconductor device includes a control circuit configured to generate a data reset signal which is enabled in response to a reset signal and first and second transfer control signals which are sequentially enabled in synchronization with a divided clock in response to a read signal and a trigger circuit configured to drive a driving signal depending on a logic level of latch data in synchronization with delayed clocks in response to the first and second transfer control signals, the driving signal having a fixed logic level based on the data reset signal being enabled.

Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

Abstract: A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.

Abstract: According to an embodiment, a semiconductor device may be provided. The semiconductor device may include an internal clock generation circuit configured to generate a plurality of internal clock signals respectively from a plurality of division clock signals. The semiconductor device may include a data input and output (I/O) circuit configured to output input data as output data in synchronization with the plurality of internal clock signals. Each bit of the output data may be outputted in sequential order in synchronization with an internal clock signal from the plurality of internal clock signals.

Abstract: According to an embodiment, a semiconductor device may be provided. The semiconductor device may include an internal clock generation circuit configured to generate a plurality of internal clock signals respectively from a plurality of division clock signals. The semiconductor device may include a data input and output (I/O) circuit configured to output input data as output data in synchronization with the plurality of internal clock signals. Each bit of the output data may be outputted in sequential order in synchronization with an internal clock signal from the plurality of internal clock signals.

Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.

Abstract: A semiconductor device may include a strobe signal buffer, a strobe signal division circuit, and a drive control circuit. The strobe signal buffer may buffer a first data strobe signal and a second data strobe signal to generate a buffer output signal and an inverted buffer output signal. The strobe signal division circuit may divide the buffer output signal and the inverted buffer output signal to generate internal strobe signals which are used in capturing data when receiving data. The drive control circuit may drive the buffer output signal to a predetermined logic level during an initial section of time from a point of time when a write operation is performed.

Abstract: A separator for secondary batteries is disclosed. The separator includes a separator main body and a coating layer disposed on the separator main body and including a first particle having a first melting point and a second particle having a second melting point that is higher than the first melting point.