Abstract: A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. The valid command generation circuit may be configured to generate a valid command for executing a predetermined function from the latch control signal. The training control circuit may be configured to generate a training result signal from the latch chip selection signal or the latch control signal based on a flag.

Abstract: A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.

Abstract: A duty correction device may be provided. The duty correction device may include a duty controller configured to output a control signal by controlling a duty of a duty corrected signal, and detect a level of a feedback signal to convert the duty based on a code signal which is applied at a section where the level of the feedback signal corresponds to a logic level. The duty correction device may include a power gating circuit configured to generate the feedback signal by driving the control signal.

Abstract: A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. The valid command generation circuit may be configured to generate a valid command for executing a predetermined function from the latch control signal. The training control circuit may be configured to generate a training result signal from the latch chip selection signal or the latch control signal based on a flag.

Abstract: A duty correction device may be provided. The duty correction device may include a duty controller configured to output a control signal by controlling a duty of a duty corrected signal, and detect a level of a feedback signal to convert the duty based on a code signal which is applied at a section where the level of the feedback signal corresponds to a logic level. The duty correction device may include a power gating circuit configured to generate the feedback signal by driving the control signal.

Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.

Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.

Abstract: A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.

Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.

Abstract: A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.

Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.

Abstract: A semiconductor device may include a strobe signal buffer, a strobe signal division circuit, and a drive control circuit. The strobe signal buffer may buffer a first data strobe signal and a second data strobe signal to generate a buffer output signal and an inverted buffer output signal. The strobe signal division circuit may divide the buffer output signal and the inverted buffer output signal to generate internal strobe signals which are used in capturing data when receiving data. The drive control circuit may drive the buffer output signal to a predetermined logic level during an initial section of time from a point of time when a write operation is performed.

Abstract: An antenna for satellite communication includes; a signal transmitting and receiving unit for receiving or transmitting a signal from/to the satellite; a driving unit for rotating the signal transmitting and receiving unit so as to enable the signal transmitting and receiving unit to track the satellite; an anti-vibration unit provided inside the posts for elastically supporting the signal transmitting and receiving unit or the driving unit. Therefore, by providing the anti-vibration unit inside the posts, it is possible to increase availability for a circumferential space of the posts and to simplify the structure of the anti-vibration unit.

Abstract: A portable test apparatus may be provided. The portable test apparatus may include a socket board configured to allow mounting of a semiconductor apparatus decapsulated for package testing. The portable test apparatus may include a test logic board electrically coupled to the socket board, the test logic board configured to perform a test on the semiconductor apparatus and for analyzing a test result. The test logic board may receive power through the socket board. The test logic board may be configured for receiving a command from outside the test apparatus, generating and analyzing a test pattern, and outputting the test result.

Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.

Abstract: A separator for secondary batteries is disclosed. The separator includes a separator main body and a coating layer disposed on the separator main body and including a first particle having a first melting point and a second particle having a second melting point that is higher than the first melting point.

Abstract: A satellite antenna housing includes: a first layer; a second layer formed so as to be in contact with one side of the first layer; a third layer formed so as to be in contact with one side of the second layer and face the first layer; a fourth layer so as to be in contact with one side of the third layer and face the second layer; and a fifth layer so as to be in contact with one side of the fourth layer and face the third layer, wherein the first layer, the third layer, and the fifth layer may be formed of a material having a dielectric constant higher than that of the second layer and the fourth layer, and the second layer and the fourth layer may have a thickness greater than that of the first layer, the third layer, and the fifth layer.

Abstract: An antenna for satellite communication includes; a signal transmitting and receiving unit for receiving or transmitting a signal from/to the satellite; a driving unit for rotating the signal transmitting and receiving unit so as to enable the signal transmitting and receiving unit to track the satellite; an anti-vibration unit provided inside the posts for elastically supporting the signal transmitting and receiving unit or the driving unit. Therefore, by providing the anti-vibration unit inside the posts, it is possible to increase availability for a circumferential space of the posts and to simplify the structure of the anti-vibration unit.