Abstract: In a system including a color liquid crystal panel, a liquid crystal display drive control device for driving the panel, and a microprocessor, the display drive control device of the invention lightens the burden imposed on a microprocessor as well as reduces the power consumption of the system.

Abstract: By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI?VCOML)/?t, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH?VCI)/?t. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2.

Abstract: It is aimed at being capable of easily changing a power supply startup procedure and complying with various display devices. A power supply circuit is provided between an instruction register of a liquid crystal driver and a power supply unit. The power supply unit is not directly supplied with a setting value registered to the instruction register from a microprocessor unit. The microprocessor unit writes setting values to the instruction register without need for the time axis. To turn on the power, the time is measured inside the power supply sequencer. Set values are sequentially input to the power supply unit. The instruction register should be also capable of registering an input timing.

Abstract: In a display driving circuit according to the present invention, not all the pixel values (example : 0˜255) but only the values (example : 179˜255) of the significant partial range (N˜100%) have data of histogram of pixels of an image as a partial histogram, and when the pixel (Ds) at the significant t% rank order of the entire histogram is within the range of the partial histogram, the display driving circuit performs its operation in the same manner as in the case where it has the entire histogram, and when the pixel (Ds) is out of the range, the display driving circuit uses the range minimum value (N) in the place of the pixel of the significant t% rank order and performs its operation.

Abstract: A YUV format to be stored in a memory is selected from A or B by a format judging unit for RGB data that is the input output display data of a memory unit, based on the comparison between chrominance (U, V) difference information on horizontal two pixels and the threshold values of U difference and V difference to be resistor-set at a format judging unit. The YUV data and information of A or B that are YUV format-converted at the format conversion unit are stored in the memory. The selection of the YUV format of A or B is, when the chrominance difference information is small as compared with the threshold value the format is YUV 422 (B conversion), and when it is large the format is that the low order bits of Y, U, V of each pixel are reduced (A conversion).

Abstract: No flicker is displayed on the display screen during display of moving pictures and power consumption can be reduced by adding a high quality moving picture display function. Moreover, the number of times of transfer of moving pictures by comprising a still-picture•text•system•I/O•bus interface and a moving picture interface (external display interface), providing a display operation change register (DM) and a RAM access change register (RM) which are changed selectively depending on display content (display mode) displayed on a display device and displaying the display data on the display device via a picture memory even in the moving picture display mode.

Abstract: There is provided a display driver control circuit which is just suitable for display drive including display with a small amount of change and display with a large amount of change and can realize saving of chip area and reduction of power consumption and cost. In this display driver control circuit, memory capacity of an internal display memory is set smaller than amount of data of one display picture of a display panel as the drive object, and the display data can be transferred with the system in which externally inputted display data is once stored in the display memory and is then sent of a drive circuit to output a drive signal and with the system in which the display data is sent in direct to the drive circuit by way of no display memory to output a drive signal. Moreover, both transfer methods can be executed on the time division basis.

Abstract: No flicker is displayed on the display screen during display of moving pictures and power consumption can be reduced by adding a high quality moving picture display function. Moreover, the number of times of transfer of moving pictures by comprising a still-picture·text·system·I/O bus·interface and a moving picture interface (external display interface), providing a display operation change register (DM) and a RAM access change register (RM) which are changed selectively depending on display content (display mode) displayed on a display device and displaying the display data on the display device via a picture memory even in the moving picture display mode.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: There is provided a display driver control circuit which is just suitable for display drive including display with a small amount of change and display with a large amount of change and can realize saving of chip area and reduction of power consumption and cost. In this display driver control circuit, memory capacity of an internal display memory is set smaller than amount of data of one display picture of a display panel as the drive object, and the display data can be transferred with the system in which externally inputted display data is once stored in the display memory and is then sent of a drive circuit to output a drive signal and with the system in which the display data is sent in direct to the drive circuit by way of no display memory to output a drive signal. Moreover, both transfer methods can be executed on the time division basis.

Abstract: It is intended to reduce the number of exclusive signal interconnections for connecting a host module to a liquid crystal display driver for a sub-display, and peripheral devices, respectively. A liquid crystal display drive and control device comprises, over one semiconductor substrate, a host interface circuit, a drive circuit, and an output port. The host interface circuit is used for connection with the host module. The drive circuit generates a drive signal for driving a liquid crystal display on the basis of information inputted to the host interface circuit before outputting. The output port is capable of controlling a logic level of an output signal on the basis of the information inputted to the host interface circuit.

Abstract: In a system including a color liquid crystal panel, a drive control device for driving the panel, and a microprocessor, the drive control device reduces the burden on the microprocessor as well as power consumption. In a liquid crystal display drive control device that incorporates a memory for storing image data displayed on a color liquid crystal panel, reads out the image data sequentially from the memory, generates image signals of the three primary colors for each pixel of the panel, and outputs the image signals from external output terminals, the drive control device includes a transparency arithmetic circuit that applies calculation processing to two image data read out from built-in memory and generates data for a transparent display, supplies display data generated by the transparency arithmetic circuit to a driver, and makes the driver generate and output drive signals to the liquid crystal panel.

Abstract: In a system including a color liquid crystal panel, a liquid crystal display drive control device for driving the panel, and a microprocessor, the display drive control device of the invention lightens the burden imposed on the microprocessor as well as reduces the power consumption of the system.

Abstract: In a display driver, one scanning period is divided into a period P and a subsequent period D. In the period P, a pre-charge voltage equal to an original data voltage is applied in a time-sharing manner to data lines in one block, and in the period D after the period P, the original data voltage is applied again.

Abstract: In a display driver, a period D following a period P in one scanning period is divided into periods R, G, and B in which data voltages are applied to data lines R, G, and B, and two output orders of the data voltage such as the period R?the period G?period B and the period B?the period G?period R are switched in each two frames.

Abstract: A two-stage decode system is provided which uses a pre-stage decoder comprising a pre-stage first decoder which decodes a bit of arbitrary part of address signals and a pre-stage second decoder which decodes the remaining bits, level shifters which respectively shift the levels of outputs of the pre-stage decoder, and post-stage decoders which respectively decode the decode outputs of the respective decoders in the pre-stage decoder, which have been level-shifted by the level shifters.

Abstract: A display control device and technique for controlling displays on a display unit, in which a plurality of display segments are two-dimensionally arranged (e.g. a dot matrix type display unit), is provided. The technique is effectively applicable to a write data latch circuit of a memory for storing display data in the display control device, such as, for example, a liquid crystal display control device, a mobile electronic apparatus, etc. A display drive control technique for controlling a moving picture display mode of a display device is also provided. The display drive control circuit controls a picture display mode of a display device for displaying still pictures and moving pictures to a liquid crystal display device, such as, for example, a dot matrix type display devices, an organic EL display device, etc.

Abstract: A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.

Abstract: It is aimed at being capable of easily changing a power supply startup procedure and complying with various display devices. A power supply circuit is provided between an instruction register of a liquid crystal driver and a power supply unit. The power supply unit is not directly supplied with a setting value registered to the instruction register from a microprocessor unit. The microprocessor unit writes setting values to the instruction register without need for the time axis. To turn on the power, the time is measured inside the power supply sequencer. Set values are sequentially input to the power supply unit. The instruction register should be also capable of registering an input timing.

Abstract: By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained.