Patents by Inventor Gregory E. Howard
Gregory E. Howard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240115946Abstract: A game system operates by: receiving character attribute selection data to be associated with a game character, wherein the character attribute selection data indicates a unique subset of a set of character attributes of a character attribute database; generating, based on the character attribute selection data, display data associated with the game character; facilitating, based on the display data associated with the game character, generation of a player token NFT associated with the game character; and preventing use of the unique subset of character attributes of the character attribute database in generating other game characters. Facilitating play of a game when the player token NFT is validated.Type: ApplicationFiled: December 20, 2023Publication date: April 11, 2024Applicant: Galiant Arts, LLCInventors: Mark Meyers, Bruce E. Stuckman, John W. Howard, Brian G. Howard, Gregory Meador
-
Patent number: 10594162Abstract: A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in response to receiving an input modulated signal. The galvanic isolator can also include a resonant coupler electrically isolated from the input stage by a dielectric. The resonant coupler can be configured to filter the input RF signal and transmit an output RF signal in response to the input RF signal. The galvanic isolator can further include an output stage electrically isolated from the resonant coupler by the dielectric. The output stage can be configured to provide an output modulated signal in response to receiving the output RF signal.Type: GrantFiled: October 13, 2016Date of Patent: March 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bharadvaj Bhamidipati, Swaminathan Sankaran, Mark W. Morgan, Gregory E. Howard, Bradley A. Kramer
-
Publication number: 20170033614Abstract: A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in response to receiving an input modulated signal. The galvanic isolator can also include a resonant coupler electrically isolated from the input stage by a dielectric. The resonant coupler can be configured to filter the input RF signal and transmit an output RF signal in response to the input RF signal. The galvanic isolator can further include an output stage electrically isolated from the resonant coupler by the dielectric. The output stage can be configured to provide an output modulated signal in response to receiving the output RF signal.Type: ApplicationFiled: October 13, 2016Publication date: February 2, 2017Inventors: Bharadvaj Bhamidipati, Swaminathan Sankaran, Mark W. Morgan, Gregory E. Howard, Bradley A. Kramer
-
Patent number: 9496926Abstract: A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in response to receiving an input modulated signal. The galvanic isolator can also include a resonant coupler electrically isolated from the input stage by a dielectric. The resonant coupler can be configured to filter the input RF signal and transmit an output RF signal in response to the input RF signal. The galvanic isolator can further include an output stage electrically isolated from the resonant coupler by the dielectric. The output stage can be configured to provide an output modulated signal in response to receiving the output RF signal.Type: GrantFiled: October 10, 2013Date of Patent: November 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bharadvaj Bhamidipati, Swaminathan Sankaran, Mark W. Morgan, Gregory E. Howard, Bradley A. Kramer
-
Patent number: 9373572Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.Type: GrantFiled: October 9, 2015Date of Patent: June 21, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
-
Publication number: 20160035655Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.Type: ApplicationFiled: October 9, 2015Publication date: February 4, 2016Inventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
-
Patent number: 9240619Abstract: An apparatus is provided. The apparatus generally comprises a plurality of pairs of differential transmission lines. The plurality of pairs of differential transmission lines includes a set of pairs of differential transmission lines with each pair of differential transmission lines from the set of pairs of differential transmission lines including at least one twist to alternate current direction. Also, the plurality of differential transmission lines are arranged such that alternating current directions substantially eliminate cross-talk across the plurality of pairs of differential transmission lines.Type: GrantFiled: April 28, 2011Date of Patent: January 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Amneh Akour, Yanli Fan, Karlheinz Muth, Mark W. Morgan
-
Patent number: 9165873Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.Type: GrantFiled: September 24, 2014Date of Patent: October 20, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
-
Patent number: 9142496Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed.Type: GrantFiled: July 28, 2014Date of Patent: September 22, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
-
Publication number: 20140346887Abstract: A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in response to receiving an input modulated signal. The galvanic isolator can also include a resonant coupler electrically isolated from the input stage by a dielectric. The resonant coupler can be configured to filter the input RF signal and transmit an output RF signal in response to the input RF signal. The galvanic isolator can further include an output stage electrically isolated from the resonant coupler by the dielectric. The output stage can be configured to provide an output modulated signal in response to receiving the output RF signal.Type: ApplicationFiled: October 10, 2013Publication date: November 27, 2014Applicant: TEXAS INSTRUMENTS INCORPORTEDInventors: BHARADVAJ BHAMIDIPATI, SWAMINATHAN SANKARAN, MARK W. MORGAN, GREGORY E. HOWARD, BRADLEY A. KRAMER
-
Structure for high-speed signal integrity in semiconductor package with single-metal-layer substrate
Patent number: 8723337Abstract: A semiconductor chip (101) with bond pads (110) on a substrate (103) with rows and columns of regularly pitched metal contact pads (131). A zone comprises a first pair (131a, 131b) and a parallel second pair (131c, 131d) of contact pads, and a single contact pad (131e) for ground potential; staggered pairs of stitch pads (133) connected to respective pairs of adjacent contact pads by parallel and equal-length traces (132a, 132b, etc.). Parallel and equal-length bonding wires (120a, 120b, etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.Type: GrantFiled: November 29, 2011Date of Patent: May 13, 2014Assignee: Texas Instruments IncorporatedInventors: Gregory E. Howard, Matthew D. Romig, Marie-Solange Anne Milleron, Souvik Mukherjee -
Patent number: 8703568Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: January 26, 2012Date of Patent: April 22, 2014Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
-
Patent number: 8680403Abstract: An apparatus is provided. The apparatus comprises a substrate and a circuit trace. The substrate includes a region that is adapted to receive a discrete component, a metal layer, a dielectric layer formed over the metal layer, a window formed in the metal layer that underlies the region, and a conductive strap that extends across the window. The circuit trace is formed on the dielectric layer and is discontinuous across the region.Type: GrantFiled: September 8, 2011Date of Patent: March 25, 2014Assignee: Texas Instruments IncorporatedInventors: Gregory E. Howard, Modesto Garcia
-
Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate
Publication number: 20130134579Abstract: A semiconductor chip (101) with bond pads (110) on a substrate (103) with rows and columns of regularly pitched metal contact pads (131). A zone comprises a first pair (131a, 131b) and a parallel second pair (131c, 131d) of contact pads, and a single contact pad (131e) for ground potential; staggered pairs of stitch pads (133) connected to respective pairs of adjacent contact pads by parallel and equal-length traces (132a, 132b, etc.). Parallel and equal-length bonding wires (120a, 120b, etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Matthew D. Romig, Marie-Solange Anne Milleron, Souvik Mukherjee -
Publication number: 20130062105Abstract: An apparatus is provided. The apparatus comprises a substrate and a circuit trace. The substrate includes a region that is adapted to receive a discrete component, a metal layer, a dielectric layer formed over the metal layer, a window formed in the metal layer that underlies the region, and a conductive strap that extends across the window. The circuit trace is formed on the dielectric layer and is discontinuous across the region.Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Applicant: Texas Instruments IncorporatedInventors: Gregory E. Howard, Modesto Garcia
-
Patent number: 8309388Abstract: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim (104) towards the bulge apex (105); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.Type: GrantFiled: December 17, 2008Date of Patent: November 13, 2012Assignee: Texas Instruments IncorporatedInventors: Kurt P. Wachtler, Wei-Yan Shih, Gregory E. Howard
-
Publication number: 20120275122Abstract: An apparatus is provided. The apparatus generally comprises a plurality of pairs of differential transmission lines. The plurality of pairs of differential transmission lines includes a set of pairs of differential transmission lines with each pair of differential transmission lines from the set of pairs of differential transmission lines including at least one twist to alternate current direction. Also, the plurality of differential transmission lines are arranged such that alternating current directions substantially eliminate cross-talk across the plurality of pairs of differential transmission lines.Type: ApplicationFiled: April 28, 2011Publication date: November 1, 2012Applicant: Texas Instruments IncorporatedInventors: Gregory E. Howard, Amneh Akour, Yanli Fan, Karlheinz Muth, Mark W. Morgan
-
Patent number: 8247300Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).Type: GrantFiled: November 30, 2009Date of Patent: August 21, 2012Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Manfred Schiekofer, Scott G. Balster, Gregory E. Howard, Alfred Hausler
-
Publication number: 20120164802Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: ApplicationFiled: January 26, 2012Publication date: June 28, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
-
Patent number: 8203197Abstract: Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by thermally conductive members formed to extend over isolation regions between higher electrical resistance subregions of the first and second regions. In one form, thermal communication is done, with or without contacts, through insulating layers to metal layers formed over the substrate. In another form, thermal communication is done through a polysilicon layer formed over the substrate.Type: GrantFiled: April 12, 2010Date of Patent: June 19, 2012Assignee: Texas Instruments IncorporatedInventors: Leland Scott Swanson, Gregory E. Howard