Patents by Inventor Gregory E. Howard

Gregory E. Howard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8129246
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Patent number: 8053256
    Abstract: The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask layer (e.g., photoresist) is then formed above the adjustable film layer and is selectively patterned by a reticleless exposure system (e.g., DMD exposure system). The selective patterning subjects different regions of the etch mask layer to varying exposure times dependent upon the thickness of the underlying adjustable film. The more etching needed to provide the underlying film to a nominal thickness, the longer the exposure of the etch mask. Therefore, the resultant etch mask, after exposure, comprises a topology allowing for various degrees of selective etching of the underlying film resulting in a uniform film.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory E. Howard, Leland Swanson
  • Patent number: 8053873
    Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through substrate vias (TSVs) extend through the substrate. At least one integrated Faraday shield includes a top and a bottom electrically conducting member that are coupled by the TSVs which surround the analog subcircuit and/or the digital subcircuit. At least one voltage regulator supplies a regulated power supply voltage that is coupled to the integrated Faraday shield that surrounds the analog subcircuit.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Satyendra S Chauhan, Gregory E Howard
  • Patent number: 7989949
    Abstract: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: August 2, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Vikas Gupta, Siva P Gurrum, Gregory E Howard
  • Publication number: 20110111553
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Application
    Filed: January 13, 2011
    Publication date: May 12, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Patent number: 7892889
    Abstract: One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (1412, 1422, etc.), which adheres to the substrate, embeds the connected components. Metal posts (1431, 1432, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: February 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory E Howard, Vikas Gupta, Darvin R Edwards
  • Patent number: 7883977
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Publication number: 20100279481
    Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).
    Type: Application
    Filed: November 30, 2009
    Publication date: November 4, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Manfred Schiekofer, Scott G. Balster, Gregory E. Howard, Alfred Hausler
  • Publication number: 20100193909
    Abstract: Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by thermally conductive members formed to extend over isolation regions between higher electrical resistance subregions of the first and second regions. In one form, thermal communication is done, with or without contacts, through insulating layers to metal layers formed over the substrate. In another form, thermal communication is done through a polysilicon layer formed over the substrate.
    Type: Application
    Filed: April 12, 2010
    Publication date: August 5, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Leland Scott Swanson, Gregory E. Howard
  • Publication number: 20100167424
    Abstract: The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask layer (e.g., photoresist) is then formed above the adjustable film layer and is selectively patterned by a reticleless exposure system (e.g., DMD exposure system). The selective patterning subjects different regions of the etch mask layer to varying exposure times dependent upon the thickness of the underlying adjustable film. The more etching needed to provide the underlying film to a nominal thickness, the longer the exposure of the etch mask. Therefore, the resultant etch mask, after exposure, comprises a topology allowing for various degrees of selective etching of the underlying film resulting in a uniform film.
    Type: Application
    Filed: April 1, 2009
    Publication date: July 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Gregory E. Howard, Leland Swanson
  • Publication number: 20100167427
    Abstract: The present invention relates to a method for trimming passive devices during fabrication to account for process variations. More particularly, the present invention relates to a method by which an adjustable device layer comprised within a passive device (e.g., resistor body, capacitor electrodes) can be measured and subsequently trimmed (e.g., etched to reduce size) during processing to correct for process variations. Essentially, an operational parameter is measured for a plurality of passive devices. The measurements are used to form an adjustment map for a region of a semiconductor body (e.g., wafer) comprising information pertaining to operational parameters as a function of spatial coordinates. The adjustment map is utilized by a DMD projector configured to pattern openings into a hardmask configured over the adjustable device layer. The adjustable device layer is then etched in regions not protected by the hardmask, thereby effectively trimming the passive device according to the adjustment map.
    Type: Application
    Filed: March 12, 2009
    Publication date: July 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Gregory E. Howard, Leland Swanson
  • Patent number: 7655523
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Publication number: 20090305464
    Abstract: One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (1412, 1422, etc.), which adheres to the substrate, embeds the connected components. Metal posts (1431, 1432, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 10, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory E. HOWARD, Vikas GUPTA, Darvin R. EDWARDS
  • Publication number: 20090302438
    Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through substrate vias (TSVs) extend through the substrate. At least one integrated Faraday shield includes a top and a bottom electrically conducting member that are coupled by the TSVs which surround the analog subcircuit and/or the digital subcircuit. At least one voltage regulator supplies a regulated power supply voltage that is coupled to the integrated Faraday shield that surrounds the analog subcircuit.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 10, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: SATYENDRA SINGH CHAUHAN, GREGORY E. HOWARD
  • Publication number: 20090267223
    Abstract: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim (104) towards the bulge apex (105); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.
    Type: Application
    Filed: December 17, 2008
    Publication date: October 29, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kurt P. WACHTLER, Wei-Yan SHIH, Gregory E. HOWARD
  • Publication number: 20090267218
    Abstract: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 29, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vikas GUPTA, Siva P. GURRUM, Gregory E. HOWARD
  • Patent number: 7572679
    Abstract: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: August 11, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Vikas Gupta, Siva P. Gurrum, Gregory E. Howard
  • Publication number: 20090130805
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Application
    Filed: January 20, 2009
    Publication date: May 21, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Patent number: 7514304
    Abstract: A MOSFET device (100) in a mono-crystalline semiconductor material (101) of a first conductivity type, which comprises a source and a drain of the opposite conductivity type, each having regions of polycrystalline semiconductor (110, 120) and respective junctions (112a, 122a) in monocrystalline semiconductor. Localized buried insulator regions (113, 123) are below the polycrystalline source and drain regions, and a gate (130) between the source and drain regions is located so that the gate channel (134) is formed in bulk mono-crystalline semiconductor material. As an example, the semiconductor is silicon, the first conductivity type is p-type, and the localized buried insulator is silicon dioxide. The semiconductor material may also include silicon germanium.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory E. Howard
  • Patent number: 7508013
    Abstract: The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: March 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory E Howard, Leland Swanson