Patents by Inventor Hai Lin

Hai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990400
    Abstract: Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ya Lo, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Shao-Kuan Lee, Cheng-Chin Lee
  • Patent number: 11991824
    Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.
    Type: Grant
    Filed: September 26, 2021
    Date of Patent: May 21, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Shao-Chien Lee, Ming-Ru Chen, Cheng-Chung Lo
  • Publication number: 20240148999
    Abstract: A patient interface including a plenum chamber, a first seal-forming structure for forming a seal around the patient's mouth, and a second seal-forming structure for forming a seal around the patient's nares. The patient interface further includes at least one stopper rib disposed in the cavity of the plenum chamber spaced apart from the first seal-forming structure in a rest position. The first seal-forming structure configured to contact the at least one stopper rib in an operational position. The at least one stopper rib configured to oppose compression of the first seal-forming structure in an anterior direction. The second seal-forming structure is not configured to contact the at least one stopper rib.
    Type: Application
    Filed: March 9, 2022
    Publication date: May 9, 2024
    Inventors: Marvin Sugi HARTONO, Kyi Thu MAUNG, Lik Tze SEET, Jing CHEN, Beng Hai TAN, Han Cheng LIN, Chuan Foong LEE, Xiang Yu ONG, Shiva Kumar SHANMUGA SUNDARA, Hugh Francis Stewart THOMAS, Sebastien DEUBEL, Chee Keong ONG, Andrew James BATE, Matthew Robin WELLS, Paul Derrick WATSON, Shannon William PRIOR
  • Publication number: 20240142394
    Abstract: Disclosed are a material analysis method based on the crystal structure database, a system, a computer-readable storage medium and an application. The material analysis method includes comparing experimental pattern information obtained from examination of a to-be-tested sample with theoretical pattern information calculated from material structure data in the crystal structure database, and obtaining crystallographic information and phase composition of the to-be-tested sample through intelligent analysis. The crystallographic information include space group, unit cell parameter, and specific coordinates of atoms in unit cell. The crystal structure database has material structure data obtained by experimental measurement and/or theoretical prediction, including chemical formula, space group, unit cell parameter and specific coordinates of atoms in unit cell.
    Type: Application
    Filed: July 30, 2021
    Publication date: May 2, 2024
    Inventors: Feng PAN, Shunning LI, Cheng DONG, Wentao ZHANG, Chenxin HOU, Litao CHEN, Junjie PAN, Shisheng ZHENG, Yuan LIN, Hai LIN
  • Publication number: 20240145600
    Abstract: A semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the source electrode and the drain electrode are arranged on one side of the gate insulating layer, wherein the gate insulating layer includes multilayer oxide films stacked on each other and at least one interface layer between the multilayer oxide films, and the material of the at least one interface layer is different from the material of the oxide films.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih WEN, Yi-Lin YANG, Hai-Ching CHEN
  • Publication number: 20240136221
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
  • Publication number: 20240131222
    Abstract: The present invention relates to a transdermal photocuring forming hydrogel with biological activity. The hydrogel can release recombinant collagen with biological activity, the recombinant collagen includes a sequence as shown in SEQ ID No. 1, an amino acid sequence of the recombinant collagen includes N basic repetitive units, and each basic repetitive unit includes n1 of the following characteristic amino acid sequences: “G-Xaa1-Xaa2-G-E-Xaa3”; the 3? end and the 5? end of the basic repetitive unit are connected to form the above characteristic amino acid sequence. The recombinant collagen provided by the present invention has relatively obvious integrin binding activity, and has the effects of promoting cell adhesion, proliferation and differentiation. The hydrogel of the present invention has good biocompatibility and stable quality, which can be cured and formed in situ in a transdermal photo-crosslinking manner after injection, with simple, convenient and controllable operation.
    Type: Application
    Filed: October 8, 2023
    Publication date: April 25, 2024
    Inventors: Hai LIN, He QIU, Jing WANG, Jian WANG, Yang XU, Lu SONG, Xia YANG, Xingdong ZHANG
  • Publication number: 20240128179
    Abstract: A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.
    Type: Application
    Filed: November 8, 2022
    Publication date: April 18, 2024
    Inventors: Jyun-Hong CHEN, Chi-Hai KUO, Pu-Ju LIN, Cheng-Ta KO
  • Patent number: 11962370
    Abstract: A technique for improving wireless communication characteristics involving matching transmitter antenna patterns to receiver antenna patterns. In a specific implementation, the transmitter antenna pattern adapts to changing parameters, such as when a smartphone is initially held in a first orientation and is later held in a second orientation. Because the transmitter antenna pattern matches receiver antenna patterns, signal quality between stations improves. In some implementations, antennas are organized and mounted to maximize spatial diversity to cause peak gains in different directions.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 16, 2024
    Assignee: Extreme Networks, Inc.
    Inventors: Changming Liu, George Gang Chen, Hai Lin, Liangfu Zhang
  • Publication number: 20240115763
    Abstract: The present invention discloses a recombinant collagen protein and its use in the cartilage repair matrix. The present invention discloses a recombinant collagen protein which contains the sequence shown in SEQ ID No. 1; the amino acid sequence of the stated recombinant collagen protein comprises N basic repetitive units; the basic repetitive unit contains n1 amino acid sequences with the following characteristic: G-Xaa1-Xaa2-G-E-Xaa3; the 3? end and the 5? end of the basic repetitive unit are connected to form the amino acid sequence with the above characteristic. The recombinant collagen protein claimed by the present invention has significant integrin binding activity, has the effect of promoting cell adhesion, proliferation, differentiation, and repairing cartilage tissue defects, etc, and it has promising prospects for application.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 11, 2024
    Inventors: Hai LIN, Yang XU, Jing WANG, Zhanhong LIU, Xia YANG, Xingdong ZHANG
  • Publication number: 20240116829
    Abstract: Disclosed in the present application are a concrete protection material, and a preparation method and a construction method therefor. The concrete protection material consists of 50%-90% of a component A and 10%-50% of a component B in percentage by weight, where the component A is prepared from 30%-65% of organic silicon, 2%-5% of nano-silicon dioxide and the balance of an organic solvent in percentage by weight; and the component B is prepared from 20%-50% of an organic base and the balance of water in percentage by weight. The present application not only can form nano-particles having a strengthening effect in capillary channels of a concrete surface layer, but also can achieve a technical effect of superhydrophobicity on the concrete surface layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 11, 2024
    Applicants: NATIONAL ENGINEERING RESEARCH CENTER OF HIGH-SPEED RAILWAY CONSTRUCTION TECHNOLOGY, CHINA RAILWAY NO.4 ENGINEERING GROUP CO., LTD, ANHUI ENGINEERING MATERIAL TECHNOLOGY CO, LTD OF CTCE GROUP
    Inventors: Dongdong FAN, Hai HUANG, Jianfeng WEN, Jianwei PENG, Zhiyong WANG, Yitao CHEN, Chenhao WU, Jianan YAO, Jie TANG, Juan CHEN, Chunhong LIN, Xianzhu HU, Zhiwu YU
  • Patent number: 11955587
    Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Jeng-Ting Li, Chi-Hai Kuo, Cheng-Ta Ko, Pu-Ju Lin
  • Publication number: 20240111131
    Abstract: An optical imaging lens includes a first lens element to a fourth lens element, and each lens element has an object-side surface and an image-side surface. The first lens element has negative refracting power, an optical axis region of the object-side surface of the first lens element is convex, the third lens element has negative refracting power, and an optical axis region of the image-side surface of the fourth lens element is convex. Lens elements included by the optical imaging lens are only the four lens elements described above, and the optical imaging lens satisfies the relationship of Tmax+Tmin?700.000 ?m, Tmax is a maximum thickness of the four lens elements from the first lens element to the fourth lens element along the optical axis, Tmin is a minimum thickness of the four lens elements from the first lens element to the fourth lens element along the optical axis.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 4, 2024
    Applicant: Genius Electronic Optical (Xiamen) Co., Ltd.
    Inventors: Huabin Liao, Hai Lin, Ou Zhou, Lanlan Zhang
  • Patent number: 11948834
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11931512
    Abstract: A patient interface including a positioning and stabilizing structure that is configured to maintain a first seal-forming structure and a second seal-forming structure in a therapeutically effective position. The positioning and stabilizing structure comprises a frame coupled to the plenum chamber. The frame includes a central portion coupled to the plenum chamber outside of the cavity. The frame also includes a pair of arms that extend away from the central portion in a posterior direction past the second seal-forming structure. The pair of arms are more flexible than the central portion. The positioning and stabilizing structure also includes headgear straps coupled to the frame, which configured to provide a tensile force to the first seal-forming structure and to the second seal-forming structure into the patient's face via the frame.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: March 19, 2024
    Assignee: ResMed Pty Ltd
    Inventors: Matthew Eves, Andrew James Bate, Sebastien Deubel, Paul Derrick Watson, Matthew Robin Wells, Beng Hai Tan, Chee Keong Ong, Marvin Sugi Hartono, Han Cheng Lin
  • Patent number: 11935783
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20240088025
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 11926638
    Abstract: Provided are compounds having a tetradentate structure of that are useful as emitters in OLED applications.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 12, 2024
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Hsiao-Fan Chen, Jason Brooks, Chun Lin, Hai T. Le, Steven Kit Chow, Neetipalli Thrimurtulu
  • Publication number: 20240063552
    Abstract: Provided is a dual-polarization high-isolation Cassegrain antenna, including a main reflector, a secondary reflector and a diagonal horn feed. The diagonal horn feed includes an integrated cross-polarization coupling-structure and a diagonal horn protruding structure, where a hollow part of the diagonal horn protruding structure is diagonal horn-shaped, and a horn opening is upward. An edge line is arranged in the diagonal horn feed, and the edge line passes through the diagonal horn protruding structure and the cross-polarization coupling-structure. The cross-polarization coupling-structure includes a first port and a second port. The second port is located at a side surface of the diagonal horn feed, and an access is communicated with an edge line of a diagonal horn. The first port is located at a bottom surface of the diagonal horn feed.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 22, 2024
    Inventors: Junxiang GE, Hai LIN, Jie WANG, Boyu QI
  • Publication number: 20240051282
    Abstract: A multilayer film having coextruded layers comprising a znLLDPE-based core layer, and mLLDPE-based outer layers on each side of the core layer comprising, wherein the znLLDPE of the core layer has a density which is less than 0.005 g/cc different from a density of the mLLDPE of the outer layers, and wherein the znLLDPE of the core layer has a melting temperature which is less than 15° C. different from a melting temperature of the mLLDPE of the outer layers.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Inventors: Shen-Hsiu HUNG, Ter-Hai LIN