Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.

Abstract: Disclosed is a bamboo strip shaping method, which includes the following steps: S01: cutting a bamboo tube, and removing inner joints, outer joints and bamboo outer skin; S02: trisecting or quartering the bamboo tube in a longitudinal direction to obtain curved bamboo strips; S03: placing the curved bamboo strips in a bamboo strip shaping device for processing; S04: subjecting the curved bamboo strips to steam treatment and heating softening treatment; S05: pressing and shaping the curved bamboo strips to obtain flattened bamboo strips, and drying for a first time under a maintained pressure; S06: wetting bamboo outer skin surfaces and bamboo inner skin surfaces of the flattened bamboo strips, and drying for a second time; and S07: wetting the bamboo outer skin surfaces and the bamboo inner skin surfaces of the flattened bamboo strips, and drying for a third time.

Abstract: An electronic mechanical braking method and an electronic mechanical braking apparatus are provided, and are applicable to an intelligent vehicle, a new energy vehicle, a traditional automobile, or the like. The method includes: obtaining status information of a first control unit, where the status information is used to indicate whether the first control unit works normally, and the first control unit is configured to perform braking control on a vehicle; and when the status information indicates that the first control unit cannot work normally, performing the braking control on the vehicle by using a second control unit. A plurality of control units are used to implement electronic mechanical braking control. Therefore, when one of the control units fails, the rest of the control units may further be used to continue the control, to implement redundant braking, effectively improve a braking control effect, and improve vehicle control safety.

Abstract: Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

Abstract: Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

Abstract: A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The method includes providing a substrate; forming a stacked material structure on the substrate; and forming trenches in the stacked material structure. Bottoms of the trenches are in the first material layer, the trenches are arranged along a first direction and form an initial stacked structure sequentially including an initial first layer, an initial second layer and an initial third layer. The method also includes etching the initial third layer to form transitional third layers arranged along a second direction perpendicular to the first direction; removing a portion of the initial first layer and a portion of the initial second layer of the initial stacked structure at two sides along the second direction to form a stacked structure including a first layer, a second layer and the transitional third layers; and forming a gate structure.

Abstract: A semiconductor structure is provided in the present disclosure. The semiconductor structure includes a substrate, a plurality of fins on the substrate, a plurality of isolation structures on the substrate, each formed on a top surface of the substrate between adjacent fins, and a power rail formed in at least one isolation structure of the plurality of isolation structures and further in the substrate, where a top surface of the power rail is lower than a top surface of the plurality of fins.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The semiconductor includes a substrate; a gate structure on the substrate; and a dielectric layer on the substrate and covering sidewall surfaces of the gate structure. The dielectric layer includes an opening passing through the gate structure along a direction perpendicular to an extending direction of the gate structure. The semiconductor structure also includes a first isolation layer in the opening and with a top surface lower than a top surface of the gate structure.

Abstract: A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of fins on the substrate, and forming an isolation structure layer including a plurality of isolation structures on the substrate, each isolation structure being formed between adjacent fins. The method further includes forming a first opening by etching at least one isolation structure of the plurality of isolation structures and a portion of the substrate, and forming a power rail by filling the first opening with a conductive material, where a top surface of the power rail is lower than a top surface of the plurality of fins.

Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.

Abstract: A surveillance camera includes a housing containing a camera module, an optical reflection component, and a first driving component. The camera module has a fixed position and is disposed opposite to a reflective surface of the optical reflection component, which is disposed in a transparent portion of the housing. The reflective surface is positioned at an angle with respect to the input axis of the camera module to reflect light received through the transparent housing portion to the camera module. The camera module captures an image by detecting the light reflected to it by the reflective surface. The first driving component drives the optical reflection component to rotate the reflective surface around the input axis of the camera module, such that the camera module captures images carried by light from different directions through the transparent portion of the housing without rotation of the camera module itself.

Abstract: A Sidwf1 gene of Sesamum indicum, including two exons and an intron, is 1638 bp in total, and has a sequence represented by SEQ ID NO: 1. Also provided is a method for determining the internode length type in sesame samples, the method including: 1) extracting a genomic DNA of a sesame sample; 2) synthesizing three primers including SiSNPdwf1 F1, SiSNPdwf1 F2, and SiSNPdwf1 R; amplifying the Sidwf1 gene or an allele SiDWF1 thereof with the genomic DNA of the sesame sample as a template, with a combination of SiSNPdwf1 F1, SiSNPdwf1 F2, and SiSNPdwf1 R a combination of SiSNPdwf1 F1 and SiSNPdwf1 R, or a combination of SiSNPdwf1 F2 and SiSNPdwf1 R, as primers, thereby yielding a PCR product; and performing electrophoresis on the PCR product or sequencing the PCR product, and determining the phenotype of the sesame sample according to an electrophoresis or sequencing result.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.

Abstract: Semiconductor structure and fabrication method are provided. The semiconductor structure includes a substrate, including a first region and a second region; a plurality of fins, formed on the first region of the substrate; a first isolation structure, formed on the first region between adjacent fins and on the second region of the substrate; a second isolation structure, formed in each fin and in the first isolation structure, over the first region of the substrate; and a power rail, formed in the isolation structure and partially in the substrate of the second region.

Abstract: Semiconductor structure and fabrication method are provided. The method includes providing a substrate including a first region and a second region; forming a plurality of fins on the first region of the substrate; forming an isolation structure on the first region and the second region of the substrate; forming a gate structure across the plurality of fins and on the isolation structure at the first region; etching the isolation structure and the substrate at the second region to form a first opening; filling the first opening with a conductive material layer; and etching the gate structure till exposing the isolation structure to form a second opening in the gate structure and removing a portion of the conductive material layer in the first opening to form a power rail.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.