Patents by Inventor Hajime Sasaki

Hajime Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CAP
    Publication number: 20150353245
    Abstract: A cap body of a cap includes: a cylindrical inner wall section to be fitted into an inner wall surface of a container mouth section; an annular wall section that extends obliquely in an upper direction toward a radial-direction center integrally from an inner wall surface of the cylindrical inner wall section, has a lower wall surface of a truncated conical shape, and has a discharge hole in a radial-direction center portion; a check valve disposed above the annular wall section to open or close the discharge hole in such a manner that a valve section is detached from or seated on an annular valve seat around the discharge hole; and a guiding tubular body disposed above the check valve and having a discharge passage of contents from the discharge hole. Therefore, at the time of using the contents, the contents can be smoothly discharged to the outside.
    Type: Application
    Filed: October 10, 2014
    Publication date: December 10, 2015
    Inventors: Takaaki SAKIMURA, Masashi SASAKI, Masashi MIZUOCHI, Hajime SASAKI, Satoshi ICHIKAWA
  • Publication number: 20150311904
    Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.
    Type: Application
    Filed: June 10, 2015
    Publication date: October 29, 2015
    Inventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
  • Publication number: 20150278178
    Abstract: An information integration apparatus includes: an information acquiring means for acquiring a plurality of pieces of information from at least one device; a time tag inserting means for inserting a time tag, which indicates time when the information is acquired, in the information; a type tag inserting means for inserting a type tag, which indicates a type of the information, in the information; an information storing means for storing the information, in which the time tag and the type tag are inserted, to a storage unit; an information reading means for setting a time point and reading the information, which has the latest time tag indicative of time before the time point, for each type of the information, from the storage unit; and an information outputting means for outputting the read information to display the information by a display unit using a display method suited to the type of information.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventors: Hideki OKUDA, Hajime SASAKI, Minoru TAKAHASHI, Jun OKAMOTO, Yoshihiro MURAGAKI
  • Patent number: 9129921
    Abstract: A method of manufacturing a nitride semiconductor device, the nitride semiconductor device having an input terminal, a drain terminal, a gate terminal, and an output terminal, includes a burn-in step in which the nitride semiconductor device is heated while inputting an RF signal to the input terminal, applying a drain voltage to the drain terminal, and applying a gate voltage to the gate terminal. The burn-in step is continued until the nitride semiconductor device exhibits a decrease in gate current.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: September 8, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hajime Sasaki
  • Patent number: 9083353
    Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.
    Type: Grant
    Filed: July 27, 2013
    Date of Patent: July 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
  • Patent number: 9054168
    Abstract: A field-effect transistor includes a channel layer in which a two-dimensional electron gas is formed, an electron supply layer located on the channel layer, a source electrode located on the electron supply layer, a drain electrode located on the electron supply layer, a gate electrode located on the electron supply layer between the source electrode and the drain electrode, and an embedded layer embedded in the channel layer deeper than a two-dimensional electron gas region where the two-dimensional electron gas is formed, directly opposite an edge of the gate electrode on a side of the gate electrode toward the drain electrode. The embedded layer is a material that increases potential of the two-dimensional electron gas region.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: June 9, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoichi Kinoshita, Hajime Sasaki
  • Patent number: 8987076
    Abstract: A method of manufacturing a transistor with suppressed characteristic variations caused by gate current, and a method of manufacturing an amplifier using such a transistor are provided. The transistor includes a SiC substrate, an AlGaN barrier layer, and a GaN buffer layer grown on the SiC substrate, a source electrode and a drain electrodes located on the AlGaN barrier layer, and a gate electrode connected to the AlGaN barrier layer via a Schottky junction. In a burn-in step, a gate voltage is applied to the transistor to cause a drain current Id to flow, and a drain voltage is applied to the transistor to heat the transistor to reduce the gate current of the transistor compared to the gate current before the burn-in.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hajime Sasaki
  • Publication number: 20150064811
    Abstract: A method of manufacturing a nitride semiconductor device, the nitride semiconductor device having an input terminal, a drain terminal, a gate terminal, and an output terminal, includes a burn-in step in which the nitride semiconductor device is heated while inputting an RF signal to the input terminal, applying a drain voltage to the drain terminal, and applying a gate voltage to the gate terminal. The burn-in step is continued until the nitride semiconductor device exhibits a decrease in gate current.
    Type: Application
    Filed: May 13, 2014
    Publication date: March 5, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventor: Hajime Sasaki
  • Publication number: 20140319582
    Abstract: A field-effect transistor includes a channel layer in which a two-dimensional electron gas is formed, an electron supply layer located on the channel layer, a source electrode located on the electron supply layer, a drain electrode located on the electron supply layer, a gate electrode located on the electron supply layer between the source electrode and the drain electrode, and an embedded layer embedded in the channel layer deeper than a two-dimensional electron gas region where the two-dimensional electron gas is formed, directly opposite an edge of the gate electrode on a side of the gate electrode toward the drain electrode. The embedded layer is a material that increases potential of the two-dimensional electron gas region.
    Type: Application
    Filed: March 18, 2014
    Publication date: October 30, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoichi Kinoshita, Hajime Sasaki
  • Publication number: 20140295635
    Abstract: A method of manufacturing a transistor with suppressed characteristic variations caused by gate current, and a method of manufacturing an amplifier using such a transistor are provided. The transistor includes a SiC substrate, an AlGaN barrier layer, and a GaN buffer layer grown on the SiC substrate, a source electrode and a drain electrode located on the AlGaN barrier layer, and a gate electrode connected to the AlGaN barrier layer via a Schottky junction. In a burn-in step, a gate voltage is applied to the transistor to cause a drain current Id to flow, and a drain voltage is applied to the transistor to heat the transistor to reduce the gate current of the transistor compared to the gate current before the burn-in.
    Type: Application
    Filed: October 15, 2013
    Publication date: October 2, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventor: Hajime Sasaki
  • Patent number: 8778404
    Abstract: The present inventors discovered that the onset of galactosamine hepatopathy is suppressed by nutritional compositions comprising as essential ingredients: whey protein hydrolysates; lecithin and oils and fats high in oleic acid, which are able to improve the lipid metabolism; and palatinose having an insulin-sparing effect. Furthermore, the whey protein hydrolysate included in the nutritional compositions was found to suppress endotoxin-induced TNF-a and interleukin 6 (IL-6) production in macrophages.
    Type: Grant
    Filed: May 30, 2009
    Date of Patent: July 15, 2014
    Assignee: Meiji Co., Ltd.
    Inventors: Hisae Kume, Makoto Yamaguchi, Kenji Mizumoto, Hajime Sasaki
  • Publication number: 20140043075
    Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.
    Type: Application
    Filed: July 27, 2013
    Publication date: February 13, 2014
    Applicant: Renesas Mobile Corporation
    Inventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
  • Publication number: 20130103417
    Abstract: Provided is a medical care support system for the sharing and reusing of medical information on the basis of a workflow which is a flow of medical-related services. A workflow step that was executed prior to an ongoing workflow step is selected by using a medical information database which has registered a workflow and information of each workflow step in association with medical information; and information is inputted by medical staff in the ongoing workflow step while the medical information registered in the selected workflow step being referred to; and the medical information being referred to and the inputted information are registered in the medical information database in association with the ongoing workflow step.
    Type: Application
    Filed: June 24, 2011
    Publication date: April 25, 2013
    Applicant: Hitachi, Ltd.
    Inventors: Kumiko Seto, Kikuo Umegaki, Masayuki Ohta, Shuntaro Yui, Satoshi Mitsuyama, Kazuki Matsuzaki, Hajime Sasaki, Takuya Kamiyama, Hisaaki Ochi, Yoshihiko Nagamine, Yuji Oka
  • Publication number: 20130049007
    Abstract: A wide-bandgap semiconductor device includes: a semiconductor substrate made of a semiconductor material having a bandgap larger than 1.42 eV; a semiconductor layer on the semiconductor substrate and made of a semiconductor material having a bandgap larger than 1.42 eV; and an active region in the semiconductor layer and including a transistor, wherein the wide-bandgap semiconductor device is opaque to light in a visible light wavelength range, from a wavelength of 360 nm to a wavelength of 830 nm.
    Type: Application
    Filed: April 2, 2012
    Publication date: February 28, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hajime SASAKI
  • Publication number: 20120287131
    Abstract: In the process of a registration between first and second images captured by different image pickup apparatuses, even if corresponding parts have different pixel values, different shapes and different field of view, the registration can be carried out with high speed and high degree of precision. In order to perform the registration between the first and second images, either of the first and second images is divided into segmented regions, and given physical property values are set to the segmented regions. Further, an image (pseudo image) having similar pixel values, shapes and field of view to the other image is created, and the pseudo image and the second image that have the same features are positioned, thereby performing the registration between the first and second images.
    Type: Application
    Filed: December 16, 2010
    Publication date: November 15, 2012
    Applicant: HITACHI, LTD.
    Inventors: Kazuki Matsuzaki, Kumiko Seto, Yoshihiko Nagamine, Hajime Sasaki
  • Patent number: 8179306
    Abstract: The invention relates to a high-frequency circuit board that can efficiently radiate heat generated in a mounted electronic component without reducing the degree of freedom in design, a high-frequency circuit module including the high-frequency circuit board, and a radar apparatus including the high-frequency circuit module. A dielectric substrate (3) includes a mounting portion (4) that is disposed on one surface (3a) of the dielectric substrate (3) and on which an electronic component (2) is to be mounted, and a waveguide (5) that is formed in the dielectric substrate (3). The mounting portion (4) and the waveguide (5) are connected with each other through a heat conductor (6) having a thermal conductivity higher than that of the dielectric substrate (3).
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 15, 2012
    Assignee: Kyocera Corporation
    Inventors: Hajime Sasaki, Kazuki Hayata
  • Patent number: 8158123
    Abstract: The present invention features methods of treating a bone resorption disease or a bone generating disease, methods for prognosing and/or diagnosing a bone resorption disease or a bone generating disease, methods for identifying a compound that modulates bone resorption disease development or bone generating disease development, methods for determining the efficacy of a bone resorption disease therapy or a bone generating disease therapy, and oligonucleotide microarrays containing probes for genes involved in osteoclast development.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: April 17, 2012
    Assignee: Forsyth Dental Infirmary for Children
    Inventors: Philip Stashenko, Yoshimura Okamatsu, Hajime Sasaki, Richard Battaglino, Ulrike Späte
  • Publication number: 20110178008
    Abstract: The present inventors focused on certain nutritional compositions known to have activity of controlling blood glucose levels. These foods were administered to rats for long periods, and real-time PCR was used to analyze the expression of genes associated with lipid metabolism in the liver and adipose tissues. As a result, the present inventors found that the expression of the PPAR? gene is enhanced by these foods, and that this is accompanied by suppressed expression of fatty acid synthase and enhanced expression of a group of PPAR? target genes associated with fatty acid metabolism. The present inventors also confirmed the effect of these foods in enhancing the expression of PPAR? and adiponectin, and discovered that these foods have the activity of enhancing the production of PPAR and PPAR-associated factors.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 21, 2011
    Inventors: Hidekazu Arai, Eiji Takeda, Hajime Sasaki
  • Patent number: 7953941
    Abstract: A data processor (1) has a central processing unit (3) and a memory controller (6) capable of controlling a memory (8) to be connected to an outside. The memory has a buffer capable of temporarily holding data within an address range corresponding to a predetermined bit number on a low order side of an address signal, and a burst operation for inputting/outputting data can be carried out by a data transfer between the buffer and the outside for an access request in which an access address is changed within the address range. When causing the memory to carry out the burst operation to give an access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects an access exceeding the address range. When causing the memory to carryout the burst access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects the access exceeding the address range.
    Type: Grant
    Filed: March 20, 2010
    Date of Patent: May 31, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masayoshi Horishima, Hajime Sasaki, Takashi Koshido
  • Patent number: 7815947
    Abstract: A nutritional composition for controlling blood sugar level comprising a protein, a lipid and a carbohydrate, wherein energy percentages supplied by the protein, lipid and carbohydrate are 10 to 25%, 20 to 35% and 40 to 60%, respectively; and oleic acid in the lipid energy percentage is 60 to 90% and palatinose and/or trehalulose in the carbohydrate energy percentage is 60 to 100%, which is useful as an oral or tube feeding nutrient for nutritional management or blood sugar level control of patients suffering from diabetes and glucose intolerance, or for obesity prevention, a therapeutic diet, a diet for diabetic patients at home, an obesity preventive diet or a food with health claims.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: October 19, 2010
    Assignee: Meiji Dairies Corporation
    Inventors: Kenji Mizumoto, Hajime Sasaki, Hisae Kume, Makoto Yamaguchi