Patents by Inventor Han Chang

Han Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240096623
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer comprising an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing material and one or more selected from the group consisting of a photoacid generator, an actinic radiation absorbing additive including an iodine substituent, and a silicon-containing monomer having iodine or phenol group substituents. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.
    Type: Application
    Filed: March 17, 2023
    Publication date: March 21, 2024
    Inventors: Chieh-Hsin HSIEH, Wei-Han LAI, Ching-Yu CHANG
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20240099154
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Patent number: 11935757
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11935200
    Abstract: A method for displaying infrastructure information on a multi-focal plane augmented reality display of a vehicle includes receiving infrastructure data. The infrastructure data includes information about a location of at least one infrastructure along a route of the vehicle. The method further includes receiving vehicle-location data. The vehicle-location data includes information about a location of the vehicle. The method further includes determining a position of the vehicle relative to the location of the least one infrastructure using the infrastructure data and the vehicle-location data. The method further includes transmitting a command signal to the multi-focal plane augmented reality display to display a virtual image showing the infrastructure information of the infrastructure on the multi-focal plane augmented reality display.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: March 19, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Joseph F. Szczerba, John P. Weiss, Kai-Han Chang, Thomas A. Seder
  • Patent number: 11935889
    Abstract: A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20240086014
    Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Rungrot Kitsomboonloha, Donggeon Han, Jason N Gomez, Kyung Wook Kim, Nikolaus Hammler, Pei-En Chang, Saman Saeedi, Shih Chang Chang, Shinya Ono, Suk Won Hong, Szu-Hsien Lee, Victor H Yin, Young-Jik Jo, Yu-Heng Cheng, Joyan G Sanctis, Hongwoo Lee
  • Publication number: 20240084148
    Abstract: The present application provides a method of preparing lithium-friendly colloid paint. The method comprises functionalizing a carbon nanotube material to obtain a plurality of carbon nanotubes with functional groups; dispersing the of carbon nanotube material with functional groups in a solution containing nitrogen molecules to from the dispersion liquid to obtain a carbon nanotube precursor; heat-treating the carbon nanotube precursors to obtain a plurality of nitrogen-doped carbon nanotubes; dispersing the plurality of nitrogen-doped carbon nanotubes in an organic solvent, and adding a dispersant obtain a nitrogen-doped carbon nanotube solution precursor; and providing a polymer material colloid and a lithium salt, and uniformly mixing the nitrogen-doped carbon nanotube solution precursor, the lithium salt and the polymer material colloid.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 14, 2024
    Inventors: WEI-CHAO CHEN, PIN-HAN WANG, HONG-ZHENG LAI, TSENG-LUNG CHANG
  • Publication number: 20240087316
    Abstract: A location in a video may be specified and content related to the location may be accessed. A method for accessing the related content may include receiving a reference to a pixel location in a frame of a video feed of a filmed occurrence and accessing a spatio-temporal index corresponding to the filmed occurrence. The spatio-temporal index may index information relating to events or objects of the filmed occurrence and corresponding pixel locations at which the events or the objects are detected in the video feed. The method may further include querying the spatio-temporal index using the pixel location to determine particular information of an indexed event or an indexed object and receiving the particular information wherein the particular information indicates at least one of spatial and temporal alignment parameters for aligning the indexed event with a corresponding event in at least one other video feed of the filmed occurrence.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Inventors: Edward Shek CHAN, Yu-han CHANG, Rajiv Tharmeswaran MAHESWARAN, Jeffrey Wayne SU
  • Publication number: 20240089581
    Abstract: An electronic system including an image sensor, a face detection engine, an eye detection engine and an eye protection engine is provided. The image sensor captures an image. The face detection engine recognizes a user face in the image. The eye detection engine recognizes user eyes in the image. The eye protection engine turns off a display device when the user eyes are recognized in the image but the user face is not recognized in the image.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: HAN-CHANG LIN, GUO-ZHEN WANG, NIEN-TSE CHEN
  • Publication number: 20240087317
    Abstract: Data processing systems and methods are disclosed for augmenting video content with one or more augmentations to produce augmented video. Elements within video content may be identified by spatiotemporal indices and may have associated values. An advertiser can pay to have an augmentation added to an element that, for example, advertises the advertiser's goods and/or includes a link that, when activated, takes a user to the advertiser's website. Elements may have associated contexts that can be used to determine augmentations and element value, such as a position and/or current use of the element.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Han CHANG, Tracey Chui Ping HO, Rajiv Tharmeswaran MAHESWARAN
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20240080505
    Abstract: A method, comprising: detecting an outage of at least one functionality in a live streaming; performing an first operation toward a second user terminal; storing data of the first operation in a database of the first user terminal; and displaying an effect corresponding to the first operation during the outage. The present disclosure may store the data of operation performed by the user terminal during outage and process the operation after the outage is recovered. Therefore, the streamers and viewers may feel interested and satisfied, instead of feeling anxious, and the user experience may be enhanced.
    Type: Application
    Filed: June 23, 2023
    Publication date: March 7, 2024
    Inventors: Yung-Chi HSU, Hsing-Yu TSAI, Chia-Han CHANG, Yi-Jou LEE, Ming-Che CHENG
  • Publication number: 20240077802
    Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate. The protective layer and the photoresist layer are selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer. The protective layer includes a polymer without a nitrogen-containing moiety, and a basic quencher, an organic acid, a photoacid generator, or a thermal acid generator.
    Type: Application
    Filed: August 7, 2023
    Publication date: March 7, 2024
    Inventors: Yu-Chung SU, Tsung-Han KO, Ching-Yu CHANG
  • Publication number: 20240077914
    Abstract: A foldable electronic device includes a first body having an end and a first inclined surface, a second body having a second inclined surface, and a hinge module. The end includes an accommodating area. A virtual shaft line exists between sides of the first inclined surface and the second inclined surface that are closest to each other. The second body rotates relative to the first body through the virtual shaft line. The hinge module includes a first bracket adjacent to the first inclined surface, connected to the first body, and located in the accommodating area, a second bracket adjacent to the second inclined surface and connected to the second body, and a third bracket including a first end and a second end. The first bracket is connected to the first end through a first torsion assembly. The second bracket is connected to the second end through a second torsion assembly.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chih-Han Chang, Tsung-Ju Chiang, Chi-Hung Lin, Yen-Ting Liu
  • Patent number: 11919957
    Abstract: The disclosure provides a method for treating a subject afflicted with a tumor derived from a small cell lung cancer (SCLC) having a high tumor mutational burden (TMB) status comprising administering to the subject a monotherapy comprising an anti-PD-1 antibody or a combination therapy comprising an anti-PD-1 antibody and an anti-CTLA-4 antibody. The present disclosure also provides a method for identifying a subject suitable for treatment with an anti-PD-1 antibody or a combination therapy comprising an anti-PD-1 antibody and an anti-CTLA-4 antibody comprising measuring a TMB status of a biological sample of the subject. A high TMB status identifies the patient as suitable for treatment with an anti-PD-1 antibody or antigen-binding portion thereof. The TMB status can be determined by sequencing nucleic acids in the tumor and identifying a genomic alteration, e.g., a somatic nonsynonymous mutation, in the sequenced nucleic acids.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: March 5, 2024
    Assignee: Bristol-Myers Squibb Company
    Inventors: Prabhu Seshaiyer Bhagavatheeswaran, Nicholas Allan John Botwood, Han Chang, William J. Geese, Sabine Maier, Giovanni Selvaggi, Joseph Daniel Szustakowski
  • Patent number: 11922044
    Abstract: A solution for deteriorated non-volatile memory is shown. When a controller determines that raw data read from the non-volatile memory is undesirable data, the controller performs safety moving of valid data of an erasure unit that contains the raw data to safely move the valid data of the erasure unit, wherein the erasure unit is a high-risk block, and the raw data in the non-volatile memory is regarded as being in a deteriorated physical address. Prior to being moved in the safety moving, the raw data is changed so that it is different from the undesirable data. In an exemplary embodiment, the undesirable data is all-1's data or all-0's data.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 5, 2024
    Assignee: SILICON MOTION, INC.
    Inventors: Yu-Hao Chang, Yu-Han Hsiao, Po-Sheng Chou
  • Patent number: 11923435
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Han Wu, Kai-Kuen Chang, Ping-Hung Chiang
  • Patent number: 11923253
    Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-luan Lin