Abstract: A semiconductor device includes a compound semiconductor layer, an oxide layer over and contacting the compound semiconductor layer, a nitride layer over and contacting the oxide layer, and a dielectric layer over and contacting the nitride layer. At least a portion of the oxide layer comprises a first crystalline structure. At least a portion of the nitride layer comprises a second crystalline structure.

Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a laminated capacitor dielectric layer including alternating layers of high-k dielectric material and high-energy band gap material, and a method of formation. In some embodiments, the MIM capacitor has a laminated capacitor dielectric layer disposed over a capacitor bottom metal layer. The laminated capacitor dielectric layer includes a first layer of a first dielectric material, a second layer of a second dielectric material disposed on top of the first layer, a third layer of a third dielectric material disposed on top of the second layer, and a fourth layer of a fourth dielectric material disposed on top of the third layer. The first and third dielectric materials have a differing capacitance and band gap energy as compared to the second and fourth dielectric materials. A capacitor top metal layer is disposed over the laminated capacitor dielectric layer.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: A method includes forming a first III-V compound layer over a substrate; forming a second III-V compound layer over the first III-V compound layer, wherein the first and second III-V compound layers include different materials; forming a first crystalline oxide layer over the second III-V compound layer; and forming a first crystalline interfacial layer over the first crystalline oxide layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a transistor device. The method may be performed by forming an anode and a cathode over an electron supply layer disposed on a semiconductor material. A doped III-N semiconductor material is formed over the electron supply layer, and an insulating material is formed over the electron supply layer and the doped III-N semiconductor material. The insulating material continuously extends from over the anode to over the cathode. The insulating material is patterned to form sidewalls of the insulating material that define an opening over the doped III-N semiconductor material. A gate structure is formed directly between the sidewalls of the insulating material and over the doped III-N semiconductor material.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: A method includes forming a first III-V compound layer over a substrate; forming a second III-V compound layer over the first III-V compound layer, wherein the first and second III-V compound layers include different materials; forming a first crystalline oxide layer over the second III-V compound layer; and forming a first crystalline interfacial layer over the first crystalline oxide layer.

Abstract: A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The HEMT includes a first III-V compound layer having a first band gap and a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap. The HEMT further includes a first oxide layer over the second III-V compound layer; a first interfacial layer over the first oxide layer; and a passivation layer over the first interfacial layer.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: The present disclosure, in some embodiments relates to a semiconductor device. The semiconductor device includes a layer of semiconductor material disposed over a substrate and an electron supply layer disposed over the layer of semiconductor material between an anode terminal and a cathode terminal. A layer of III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer contacts an upper surface of the electron supply layer and further contacts an upper surface and a sidewall of the layer of III-N semiconductor material. A gate structure is separated from the layer of III-N semiconductor material by the passivation layer.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress.

Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.

Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.